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authorJanne Grunau <j@jannau.net>2022-12-07 01:38:46 +0300
committerHector Martin <marcan@marcan.st>2022-12-07 04:17:18 +0300
commit9ecb7a4b8ac67c1a73fefd17bc00e943d7f74378 (patch)
treec6505e6943207f1b39a36371ef9ee75eaa7c70f3 /arch/arm64
parent63bf0b66ddfa6761dd47350b8d1f7161a06e9954 (diff)
downloadlinux-9ecb7a4b8ac67c1a73fefd17bc00e943d7f74378.tar.xz
arm64: dts: apple: Add t8103 L1/L2 cache properties and nodes
The t8103 CPU nodes are missing the cache hierarchy information. The cache hierarchy on Arm can not be detected and needs to be described in DT. The OS scheduler can make use of this information for scheduling decisions. The cache size information is based on various articles about the processors. There's also an L3 system level cache (SLC). It's not described here because SLCs typically have some MMIO interface which would need to be described. Based on Rob Herring's patch adding cache properties and nodes for t600x. Link: https://lore.kernel.org/asahi/20221122220619.659174-1-robh@kernel.org/ Signed-off-by: Janne Grunau <j@jannau.net> Signed-off-by: Hector Martin <marcan@marcan.st>
Diffstat (limited to 'arch/arm64')
-rw-r--r--arch/arm64/boot/dts/apple/t8103.dtsi38
1 files changed, 38 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/apple/t8103.dtsi
index 264bd0bae567..9859219699f4 100644
--- a/arch/arm64/boot/dts/apple/t8103.dtsi
+++ b/arch/arm64/boot/dts/apple/t8103.dtsi
@@ -63,6 +63,9 @@
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
cpu_e1: cpu@1 {
@@ -74,6 +77,9 @@
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
cpu_e2: cpu@2 {
@@ -85,6 +91,9 @@
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
cpu_e3: cpu@3 {
@@ -96,6 +105,9 @@
operating-points-v2 = <&ecluster_opp>;
capacity-dmips-mhz = <714>;
performance-domains = <&cpufreq_e>;
+ next-level-cache = <&l2_cache_0>;
+ i-cache-size = <0x20000>;
+ d-cache-size = <0x10000>;
};
cpu_p0: cpu@10100 {
@@ -107,6 +119,9 @@
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
cpu_p1: cpu@10101 {
@@ -118,6 +133,9 @@
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
cpu_p2: cpu@10102 {
@@ -129,6 +147,9 @@
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
};
cpu_p3: cpu@10103 {
@@ -140,6 +161,23 @@
operating-points-v2 = <&pcluster_opp>;
capacity-dmips-mhz = <1024>;
performance-domains = <&cpufreq_p>;
+ next-level-cache = <&l2_cache_1>;
+ i-cache-size = <0x30000>;
+ d-cache-size = <0x20000>;
+ };
+
+ l2_cache_0: l2-cache-0 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0x400000>;
+ };
+
+ l2_cache_1: l2-cache-1 {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-unified;
+ cache-size = <0xc00000>;
};
};