diff options
| author | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-10-08 19:48:27 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-10-08 19:48:27 +0300 |
| commit | ddf92a2ebaa11a494946f6f153a23d36b7801d5b (patch) | |
| tree | 2981a5732a586b3e83ce4e33ec529138abbbba64 /arch/arm | |
| parent | 3b232d34011a152832ba40289e9d476dfcb846d2 (diff) | |
| parent | 7aa21fec187b7bc2a55be4daad4585098e2f47df (diff) | |
| download | linux-ddf92a2ebaa11a494946f6f153a23d36b7801d5b.tar.xz | |
Merge v6.11.2
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/arm')
233 files changed, 4879 insertions, 4476 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ee5115252aac..173159e93c99 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -34,6 +34,7 @@ config ARM select ARCH_MIGHT_HAVE_PC_PARPORT select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 + select ARCH_NEED_CMPXCHG_1_EMU if CPU_V6 select ARCH_SUPPORTS_ATOMIC_RMW select ARCH_SUPPORTS_CFI_CLANG select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE @@ -86,6 +87,7 @@ config ARM select HAVE_ARCH_PFN_VALID select HAVE_ARCH_SECCOMP select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT + select HAVE_ARCH_STACKLEAK select HAVE_ARCH_THREAD_STRUCT_WHITELIST select HAVE_ARCH_TRACEHOOK select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE @@ -115,6 +117,7 @@ config ARM select HAVE_KERNEL_XZ select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M select HAVE_KRETPROBES if HAVE_KPROBES + select HAVE_LD_DEAD_CODE_DATA_ELIMINATION if (LD_VERSION >= 23600 || LD_IS_LLD) select HAVE_MOD_ARCH_SPECIFIC select HAVE_NMI select HAVE_OPTPROBES if !THUMB2_KERNEL @@ -735,7 +738,7 @@ config ARM_ERRATA_764319 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction" depends on CPU_V7 help - This option enables the workaround for the 764319 Cortex A-9 erratum. + This option enables the workaround for the 764319 Cortex-A9 erratum. CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an unexpected Undefined Instruction exception when the DBGSWENABLE external pin is set to 0, even when the CP14 accesses are performed @@ -1482,7 +1485,8 @@ config ARM_ATAG_DTB_COMPAT from the ATAG list and store it at run time into the appended DTB. choice - prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT + prompt "Kernel command line type" + depends on ARM_ATAG_DTB_COMPAT default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER @@ -1511,7 +1515,8 @@ config CMDLINE memory size and the root device (e.g., mem=64M root=/dev/nfs). choice - prompt "Kernel command line type" if CMDLINE != "" + prompt "Kernel command line type" + depends on CMDLINE != "" default CMDLINE_FROM_BOOTLOADER config CMDLINE_FROM_BOOTLOADER diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile index 6bca03c0c7f0..945b5975fce2 100644 --- a/arch/arm/boot/compressed/Makefile +++ b/arch/arm/boot/compressed/Makefile @@ -9,6 +9,7 @@ OBJS = HEAD = head.o OBJS += misc.o decompress.o +CFLAGS_decompress.o += $(DISABLE_STACKLEAK_PLUGIN) ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y) OBJS += debug.o AFLAGS_head.o += -DDEBUG diff --git a/arch/arm/boot/compressed/vmlinux.lds.S b/arch/arm/boot/compressed/vmlinux.lds.S index 3fcb3e62dc56..d411abd4310e 100644 --- a/arch/arm/boot/compressed/vmlinux.lds.S +++ b/arch/arm/boot/compressed/vmlinux.lds.S @@ -125,7 +125,7 @@ SECTIONS . = BSS_START; __bss_start = .; - .bss : { *(.bss) } + .bss : { *(.bss .bss.*) } _end = .; . = ALIGN(8); /* the stack must be 64-bit aligned */ diff --git a/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi index a79e1d1d30a7..7f62aef9ca8a 100644 --- a/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-eb-bbrevd.dtsi @@ -22,7 +22,7 @@ / { /* Introduce a fixed regulator for the new ethernet controller */ - veth: fixedregulator@0 { + veth: regulator-veth { compatible = "regulator-fixed"; regulator-name = "veth"; regulator-min-microvolt = <3300000>; diff --git a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi index fbb2258b451f..16f784da5a55 100644 --- a/arch/arm/boot/dts/arm/arm-realview-eb.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-eb.dtsi @@ -45,7 +45,7 @@ }; /* The voltage to the MMC card is hardwired at 3.3V */ - vmmc: fixedregulator@0 { + vmmc: regulator-vmmc { compatible = "regulator-fixed"; regulator-name = "vmmc"; regulator-min-microvolt = <3300000>; @@ -53,13 +53,13 @@ regulator-boot-on; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -67,48 +67,8 @@ clocks = <&xtal24mhz>; }; - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts index d99bac02232b..b9b10cbd65aa 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb1176.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb1176.dts @@ -63,13 +63,13 @@ regulator-boot-on; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: mclk: kmiclk: sspclk: uartclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -77,40 +77,8 @@ clocks = <&xtal24mhz>; }; - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts index 89103d54ecc1..ce35748f3d25 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts +++ b/arch/arm/boot/dts/arm/arm-realview-pb11mp.dts @@ -163,19 +163,19 @@ regulator-boot-on; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - refclk32khz: refclk32khz { + refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -183,48 +183,8 @@ clocks = <&xtal24mhz>; }; - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; diff --git a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi index ec1507c5147c..e625403a9456 100644 --- a/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi +++ b/arch/arm/boot/dts/arm/arm-realview-pbx.dtsi @@ -62,19 +62,19 @@ regulator-boot-on; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: mclk: kmiclk: sspclk: uartclk: wdogclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - refclk32khz: refclk32khz { + refclk32khz: clock-32768 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <32768>; }; - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -82,48 +82,8 @@ clocks = <&xtal24mhz>; }; - mclk: mclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - kmiclk: kmiclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - sspclk: sspclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - uartclk: uartclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - - wdogclk: wdogclk@24M { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* FIXME: this actually hangs off the PLL clocks */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; diff --git a/arch/arm/boot/dts/arm/integratorap-im-pd1.dts b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts index 367850ea0912..db13e09f2fab 100644 --- a/arch/arm/boot/dts/arm/integratorap-im-pd1.dts +++ b/arch/arm/boot/dts/arm/integratorap-im-pd1.dts @@ -54,7 +54,7 @@ }; /* Also used for the Smart Card Interface SCI */ - impd1_uartclk: clock@1_4 { + impd1_uartclk: clock-uart { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <4>; @@ -64,7 +64,7 @@ }; /* For the SSP the clock is divided by 64 */ - impd1_sspclk: clock@1_64 { + impd1_sspclk: clock-ssp { compatible = "fixed-factor-clock"; #clock-cells = <0>; clock-div = <64>; diff --git a/arch/arm/boot/dts/arm/integratorap.dts b/arch/arm/boot/dts/arm/integratorap.dts index d9927d3181dc..9b6a1dbaf265 100644 --- a/arch/arm/boot/dts/arm/integratorap.dts +++ b/arch/arm/boot/dts/arm/integratorap.dts @@ -57,22 +57,14 @@ }; /* 24 MHz chrystal on the Integrator/AP development board */ - xtal24mhz: xtal24mhz@24M { + xtal24mhz: pclk: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; }; - pclk: pclk@0 { - #clock-cells = <0>; - compatible = "fixed-factor-clock"; - clock-div = <1>; - clock-mult = <1>; - clocks = <&xtal24mhz>; - }; - /* The UART clock is 14.74 MHz divided by an ICS525 */ - uartclk: uartclk@14.74M { + uartclk: clock-14745600 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <14745600>; @@ -81,7 +73,7 @@ core-module@10000000 { /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { + cm24mhz: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; diff --git a/arch/arm/boot/dts/arm/integratorcp.dts b/arch/arm/boot/dts/arm/integratorcp.dts index c011333eb165..8ad1a8957ace 100644 --- a/arch/arm/boot/dts/arm/integratorcp.dts +++ b/arch/arm/boot/dts/arm/integratorcp.dts @@ -47,14 +47,14 @@ */ /* The codec chrystal operates at 24.576 MHz */ - xtal_codec: xtal24.576@24.576M { + xtal_codec: clock-24576000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24576000>; }; /* The chrystal is divided by 2 by the codec for the AACI bit clock */ - aaci_bitclk: aaci_bitclk@12.288M { + aaci_bitclk: clock-12288000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <2>; @@ -63,21 +63,21 @@ }; /* This is a 25MHz chrystal on the base board */ - xtal25mhz: xtal25mhz@25M { + xtal25mhz: clock-25000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <25000000>; }; /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ - uartclk: uartclk@14.74M { + uartclk: clock-14745600 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <14745600>; }; /* Actually sysclk I think */ - pclk: pclk@0 { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <0>; @@ -85,7 +85,7 @@ core-module@10000000 { /* 24 MHz chrystal on the core module */ - cm24mhz: cm24mhz@24M { + cm24mhz: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -131,7 +131,7 @@ }; /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; diff --git a/arch/arm/boot/dts/arm/mps2.dtsi b/arch/arm/boot/dts/arm/mps2.dtsi index ce308820765b..e240bc8aa605 100644 --- a/arch/arm/boot/dts/arm/mps2.dtsi +++ b/arch/arm/boot/dts/arm/mps2.dtsi @@ -48,37 +48,37 @@ #address-cells = <1>; #size-cells = <1>; - oscclk0: clk-osc0 { + oscclk0: clock-50000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <50000000>; }; - oscclk1: clk-osc1 { + oscclk1: clock-24576000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24576000>; }; - oscclk2: clk-osc2 { + oscclk2: clock-25000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <25000000>; }; - cfgclk: clk-cfg { + cfgclk: clock-5000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <5000000>; }; - spicfgclk: clk-spicfg { + spicfgclk: clock-75000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <75000000>; }; - sysclk: clk-sys { + sysclk: spiclcd: spicon: i2cclcd: i2caud: clock-sys { compatible = "fixed-factor-clock"; clocks = <&oscclk0>; #clock-cells = <0>; @@ -86,7 +86,7 @@ clock-mult = <1>; }; - audmclk: clk-audm { + audmclk: clk-12388000 { compatible = "fixed-factor-clock"; clocks = <&oscclk1>; #clock-cells = <0>; @@ -94,7 +94,7 @@ clock-mult = <1>; }; - audsclk: clk-auds { + audsclk: clk-3072000 { compatible = "fixed-factor-clock"; clocks = <&oscclk1>; #clock-cells = <0>; @@ -102,38 +102,6 @@ clock-mult = <1>; }; - spiclcd: clk-cpiclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - spicon: clk-spicon { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2cclcd: clk-i2cclcd { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - i2caud: clk-i2caud { - compatible = "fixed-factor-clock"; - clocks = <&oscclk0>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - soc { compatible = "simple-bus"; ranges; diff --git a/arch/arm/boot/dts/arm/versatile-ab.dts b/arch/arm/boot/dts/arm/versatile-ab.dts index de45aa99e260..635ab9268899 100644 --- a/arch/arm/boot/dts/arm/versatile-ab.dts +++ b/arch/arm/boot/dts/arm/versatile-ab.dts @@ -24,7 +24,7 @@ reg = <0x0 0x08000000>; }; - xtal24mhz: xtal24mhz@24M { + xtal24mhz: clock-24000000 { #clock-cells = <0>; compatible = "fixed-clock"; clock-frequency = <24000000>; @@ -142,14 +142,14 @@ }; /* OSC1 on AB, OSC4 on PB */ - osc1: cm_aux_osc@24M { + osc1: clock-osc { #clock-cells = <0>; compatible = "arm,versatile-cm-auxosc"; clocks = <&xtal24mhz>; }; /* The timer clock is the 24 MHz oscillator divided to 1MHz */ - timclk: timclk@1M { + timclk: clock-1000000 { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <24>; @@ -157,7 +157,7 @@ clocks = <&xtal24mhz>; }; - pclk: pclk@24M { + pclk: clock-pclk { #clock-cells = <0>; compatible = "fixed-factor-clock"; clock-div = <1>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi index 8af4b77fe655..158b3923eae3 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi +++ b/arch/arm/boot/dts/arm/vexpress-v2m-rs1.dtsi @@ -20,7 +20,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> / { - v2m_fixed_3v3: fixed-regulator-0 { + v2m_fixed_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; @@ -28,21 +28,21 @@ regulator-always-on; }; - v2m_clk24mhz: clk24mhz { + v2m_clk24mhz: clock-24000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; - v2m_refclk1mhz: refclk1mhz { + v2m_refclk1mhz: clock-1000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; - v2m_refclk32khz: refclk32khz { + v2m_refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2m.dtsi b/arch/arm/boot/dts/arm/vexpress-v2m.dtsi index c5e92f6d2fcd..be03f2a8a57a 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/arm/vexpress-v2m.dtsi @@ -351,7 +351,7 @@ }; }; - v2m_fixed_3v3: fixed-regulator-0 { + v2m_fixed_3v3: regulator-3v3 { compatible = "regulator-fixed"; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; @@ -359,21 +359,21 @@ regulator-always-on; }; - v2m_clk24mhz: clk24mhz { + v2m_clk24mhz: clock-24000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <24000000>; clock-output-names = "v2m:clk24mhz"; }; - v2m_refclk1mhz: refclk1mhz { + v2m_refclk1mhz: clock-1000000 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <1000000>; clock-output-names = "v2m:refclk1mhz"; }; - v2m_refclk32khz: refclk32khz { + v2m_refclk32khz: clock-32768 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -436,7 +436,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0 { + clock-controller-0 { /* MCC static memory clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -445,7 +445,7 @@ clock-output-names = "v2m:oscclk0"; }; - v2m_oscclk1: oscclk1 { + v2m_oscclk1: clock-controller-1 { /* CLCD clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -454,7 +454,7 @@ clock-output-names = "v2m:oscclk1"; }; - v2m_oscclk2: oscclk2 { + v2m_oscclk2: clock-controller-2 { /* IO FPGA peripheral clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -463,7 +463,7 @@ clock-output-names = "v2m:oscclk2"; }; - volt-vio { + regulator-vio { /* Logic level voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts index 679537e17ff5..5a91e936edef 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca15-tc1.dts @@ -142,7 +142,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0 { + clock-controller-0 { /* CPU PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -151,7 +151,7 @@ clock-output-names = "oscclk0"; }; - oscclk4 { + clock-controller-4 { /* Multiplexed AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -160,7 +160,7 @@ clock-output-names = "oscclk4"; }; - hdlcd_clk: oscclk5 { + hdlcd_clk: clock-controller-5 { /* HDLCD PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; @@ -169,7 +169,7 @@ clock-output-names = "oscclk5"; }; - smbclk: oscclk6 { + smbclk: clock-controller-6 { /* SMB clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 6>; @@ -178,7 +178,7 @@ clock-output-names = "oscclk6"; }; - sys_pll: oscclk7 { + sys_pll: clock-controller-7 { /* SYS PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 7>; @@ -187,7 +187,7 @@ clock-output-names = "oscclk7"; }; - oscclk8 { + clock-controller-8 { /* DDR2 PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 8>; @@ -196,7 +196,7 @@ clock-output-names = "oscclk8"; }; - volt-cores { + regulator-cores { /* CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts index 511e87cc2bc5..6ef23c53d2d8 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca15_a7.dts @@ -253,7 +253,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0 { + clock-controller-0 { /* A15 PLL 0 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -262,7 +262,7 @@ clock-output-names = "oscclk0"; }; - oscclk1 { + clock-controller-1 { /* A15 PLL 1 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -271,7 +271,7 @@ clock-output-names = "oscclk1"; }; - oscclk2 { + clock-controller-2 { /* A7 PLL 0 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -280,7 +280,7 @@ clock-output-names = "oscclk2"; }; - oscclk3 { + clock-controller-3 { /* A7 PLL 1 reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 3>; @@ -289,7 +289,7 @@ clock-output-names = "oscclk3"; }; - oscclk4 { + clock-controller-4 { /* External AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -298,7 +298,7 @@ clock-output-names = "oscclk4"; }; - hdlcd_clk: oscclk5 { + hdlcd_clk: clock-controller-5 { /* HDLCD PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; @@ -307,7 +307,7 @@ clock-output-names = "oscclk5"; }; - smbclk: oscclk6 { + smbclk: clock-controller-6 { /* Static memory controller clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 6>; @@ -316,7 +316,7 @@ clock-output-names = "oscclk6"; }; - oscclk7 { + clock-controller-7 { /* SYS PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 7>; @@ -325,7 +325,7 @@ clock-output-names = "oscclk7"; }; - oscclk8 { + clock-controller-8 { /* DDR2 PLL reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 8>; @@ -334,7 +334,7 @@ clock-output-names = "oscclk8"; }; - volt-a15 { + regulator-a15 { /* A15 CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -345,7 +345,7 @@ label = "A15 Vcore"; }; - volt-a7 { + regulator-a7 { /* A7 CPU core voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 1>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts index ff1f9a1bcfcf..e3896253f33e 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca5s.dts @@ -145,7 +145,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - cpu_clk: oscclk0 { + cpu_clk: clock-controller-0 { /* CPU and internal AXI reference clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -154,7 +154,7 @@ clock-output-names = "oscclk0"; }; - axi_clk: oscclk1 { + axi_clk: clock-controller-1 { /* Multiplexed AXI master clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -163,7 +163,7 @@ clock-output-names = "oscclk1"; }; - oscclk2 { + clock-controller-2 { /* DDR2 */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -172,7 +172,7 @@ clock-output-names = "oscclk2"; }; - hdlcd_clk: oscclk3 { + hdlcd_clk: clock-controller-3 { /* HDLCD */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 3>; @@ -181,7 +181,7 @@ clock-output-names = "oscclk3"; }; - oscclk4 { + clock-controller-4 { /* Test chip gate configuration */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 4>; @@ -190,7 +190,7 @@ clock-output-names = "oscclk4"; }; - smbclk: oscclk5 { + smbclk: clock-controller-5 { /* SMB clock */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 5>; diff --git a/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts b/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts index 8bf35666412b..43a5a4ab6ff0 100644 --- a/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts +++ b/arch/arm/boot/dts/arm/vexpress-v2p-ca9.dts @@ -187,7 +187,7 @@ compatible = "arm,vexpress,config-bus"; arm,vexpress,config-bridge = <&v2m_sysreg>; - oscclk0: extsaxiclk { + oscclk0: clock-controller-0 { /* ACLK clock to the AXI master port on the test chip */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 0>; @@ -196,7 +196,7 @@ clock-output-names = "extsaxiclk"; }; - oscclk1: clcdclk { + oscclk1: clock-controller-1 { /* Reference clock for the CLCD */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 1>; @@ -205,7 +205,7 @@ clock-output-names = "clcdclk"; }; - smbclk: oscclk2: tcrefclk { + smbclk: oscclk2: clock-controller-2 { /* Reference clock for the test chip internal PLLs */ compatible = "arm,vexpress-osc"; arm,vexpress-sysreg,func = <1 2>; @@ -214,7 +214,7 @@ clock-output-names = "tcrefclk"; }; - volt-vd10 { + regulator-vd10 { /* Test Chip internal logic voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 0>; @@ -223,7 +223,7 @@ label = "VD10"; }; - volt-vd10-s2 { + regulator-vd10-s2 { /* PL310, L2 cache, RAM cell supply (not PL310 logic) */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 1>; @@ -232,7 +232,7 @@ label = "VD10_S2"; }; - volt-vd10-s3 { + regulator-vd10-s3 { /* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 2>; @@ -241,7 +241,7 @@ label = "VD10_S3"; }; - volt-vcc1v8 { + regulator-vcc1v8 { /* DDR2 SDRAM and Test Chip DDR2 I/O supply */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 3>; @@ -250,7 +250,7 @@ label = "VCC1V8"; }; - volt-ddr2vtt { + regulator-ddr2vtt { /* DDR2 SDRAM VTT termination voltage */ compatible = "arm,vexpress-volt"; arm,vexpress-sysreg,func = <2 4>; @@ -259,7 +259,7 @@ label = "DDR2VTT"; }; - volt-vcc3v3 { + regulator-vcc3v3 { /* Local board supply for miscellaneous logic external to the Test Chip */ arm,vexpress-sysreg,func = <2 5>; compatible = "arm,vexpress-volt"; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi index 857cb26ed6d7..c669ec202085 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g4.dtsi @@ -463,7 +463,7 @@ interrupt-controller; }; - i2c0: i2c-bus@40 { + i2c0: i2c@40 { #address-cells = <1>; #size-cells = <0>; @@ -478,7 +478,7 @@ /* Does not need pinctrl properties */ }; - i2c1: i2c-bus@80 { + i2c1: i2c@80 { #address-cells = <1>; #size-cells = <0>; @@ -493,7 +493,7 @@ /* Does not need pinctrl properties */ }; - i2c2: i2c-bus@c0 { + i2c2: i2c@c0 { #address-cells = <1>; #size-cells = <0>; @@ -509,7 +509,7 @@ status = "disabled"; }; - i2c3: i2c-bus@100 { + i2c3: i2c@100 { #address-cells = <1>; #size-cells = <0>; @@ -525,7 +525,7 @@ status = "disabled"; }; - i2c4: i2c-bus@140 { + i2c4: i2c@140 { #address-cells = <1>; #size-cells = <0>; @@ -541,7 +541,7 @@ status = "disabled"; }; - i2c5: i2c-bus@180 { + i2c5: i2c@180 { #address-cells = <1>; #size-cells = <0>; @@ -557,7 +557,7 @@ status = "disabled"; }; - i2c6: i2c-bus@1c0 { + i2c6: i2c@1c0 { #address-cells = <1>; #size-cells = <0>; @@ -573,7 +573,7 @@ status = "disabled"; }; - i2c7: i2c-bus@300 { + i2c7: i2c@300 { #address-cells = <1>; #size-cells = <0>; @@ -589,7 +589,7 @@ status = "disabled"; }; - i2c8: i2c-bus@340 { + i2c8: i2c@340 { #address-cells = <1>; #size-cells = <0>; @@ -605,7 +605,7 @@ status = "disabled"; }; - i2c9: i2c-bus@380 { + i2c9: i2c@380 { #address-cells = <1>; #size-cells = <0>; @@ -621,7 +621,7 @@ status = "disabled"; }; - i2c10: i2c-bus@3c0 { + i2c10: i2c@3c0 { #address-cells = <1>; #size-cells = <0>; @@ -637,7 +637,7 @@ status = "disabled"; }; - i2c11: i2c-bus@400 { + i2c11: i2c@400 { #address-cells = <1>; #size-cells = <0>; @@ -653,7 +653,7 @@ status = "disabled"; }; - i2c12: i2c-bus@440 { + i2c12: i2c@440 { #address-cells = <1>; #size-cells = <0>; @@ -669,7 +669,7 @@ status = "disabled"; }; - i2c13: i2c-bus@480 { + i2c13: i2c@480 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index e6f3cf3c721e..6e05cbcce49c 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -592,7 +592,7 @@ interrupt-controller; }; - i2c0: i2c-bus@40 { + i2c0: i2c@40 { #address-cells = <1>; #size-cells = <0>; @@ -607,7 +607,7 @@ /* Does not need pinctrl properties */ }; - i2c1: i2c-bus@80 { + i2c1: i2c@80 { #address-cells = <1>; #size-cells = <0>; @@ -622,7 +622,7 @@ /* Does not need pinctrl properties */ }; - i2c2: i2c-bus@c0 { + i2c2: i2c@c0 { #address-cells = <1>; #size-cells = <0>; @@ -638,7 +638,7 @@ status = "disabled"; }; - i2c3: i2c-bus@100 { + i2c3: i2c@100 { #address-cells = <1>; #size-cells = <0>; @@ -654,7 +654,7 @@ status = "disabled"; }; - i2c4: i2c-bus@140 { + i2c4: i2c@140 { #address-cells = <1>; #size-cells = <0>; @@ -670,7 +670,7 @@ status = "disabled"; }; - i2c5: i2c-bus@180 { + i2c5: i2c@180 { #address-cells = <1>; #size-cells = <0>; @@ -686,7 +686,7 @@ status = "disabled"; }; - i2c6: i2c-bus@1c0 { + i2c6: i2c@1c0 { #address-cells = <1>; #size-cells = <0>; @@ -702,7 +702,7 @@ status = "disabled"; }; - i2c7: i2c-bus@300 { + i2c7: i2c@300 { #address-cells = <1>; #size-cells = <0>; @@ -718,7 +718,7 @@ status = "disabled"; }; - i2c8: i2c-bus@340 { + i2c8: i2c@340 { #address-cells = <1>; #size-cells = <0>; @@ -734,7 +734,7 @@ status = "disabled"; }; - i2c9: i2c-bus@380 { + i2c9: i2c@380 { #address-cells = <1>; #size-cells = <0>; @@ -750,7 +750,7 @@ status = "disabled"; }; - i2c10: i2c-bus@3c0 { + i2c10: i2c@3c0 { #address-cells = <1>; #size-cells = <0>; @@ -766,7 +766,7 @@ status = "disabled"; }; - i2c11: i2c-bus@400 { + i2c11: i2c@400 { #address-cells = <1>; #size-cells = <0>; @@ -782,7 +782,7 @@ status = "disabled"; }; - i2c12: i2c-bus@440 { + i2c12: i2c@440 { #address-cells = <1>; #size-cells = <0>; @@ -798,7 +798,7 @@ status = "disabled"; }; - i2c13: i2c-bus@480 { + i2c13: i2c@480 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index 7fb421153596..0c00882f111a 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -905,7 +905,7 @@ #include "aspeed-g6-pinctrl.dtsi" &i2c { - i2c0: i2c-bus@80 { + i2c0: i2c@80 { #address-cells = <1>; #size-cells = <0>; reg = <0x80 0x80>; @@ -919,7 +919,7 @@ status = "disabled"; }; - i2c1: i2c-bus@100 { + i2c1: i2c@100 { #address-cells = <1>; #size-cells = <0>; reg = <0x100 0x80>; @@ -933,7 +933,7 @@ status = "disabled"; }; - i2c2: i2c-bus@180 { + i2c2: i2c@180 { #address-cells = <1>; #size-cells = <0>; reg = <0x180 0x80>; @@ -947,7 +947,7 @@ status = "disabled"; }; - i2c3: i2c-bus@200 { + i2c3: i2c@200 { #address-cells = <1>; #size-cells = <0>; reg = <0x200 0x80>; @@ -961,7 +961,7 @@ status = "disabled"; }; - i2c4: i2c-bus@280 { + i2c4: i2c@280 { #address-cells = <1>; #size-cells = <0>; reg = <0x280 0x80>; @@ -975,7 +975,7 @@ status = "disabled"; }; - i2c5: i2c-bus@300 { + i2c5: i2c@300 { #address-cells = <1>; #size-cells = <0>; reg = <0x300 0x80>; @@ -989,7 +989,7 @@ status = "disabled"; }; - i2c6: i2c-bus@380 { + i2c6: i2c@380 { #address-cells = <1>; #size-cells = <0>; reg = <0x380 0x80>; @@ -1003,7 +1003,7 @@ status = "disabled"; }; - i2c7: i2c-bus@400 { + i2c7: i2c@400 { #address-cells = <1>; #size-cells = <0>; reg = <0x400 0x80>; @@ -1017,7 +1017,7 @@ status = "disabled"; }; - i2c8: i2c-bus@480 { + i2c8: i2c@480 { #address-cells = <1>; #size-cells = <0>; reg = <0x480 0x80>; @@ -1031,7 +1031,7 @@ status = "disabled"; }; - i2c9: i2c-bus@500 { + i2c9: i2c@500 { #address-cells = <1>; #size-cells = <0>; reg = <0x500 0x80>; @@ -1045,7 +1045,7 @@ status = "disabled"; }; - i2c10: i2c-bus@580 { + i2c10: i2c@580 { #address-cells = <1>; #size-cells = <0>; reg = <0x580 0x80>; @@ -1059,7 +1059,7 @@ status = "disabled"; }; - i2c11: i2c-bus@600 { + i2c11: i2c@600 { #address-cells = <1>; #size-cells = <0>; reg = <0x600 0x80>; @@ -1073,7 +1073,7 @@ status = "disabled"; }; - i2c12: i2c-bus@680 { + i2c12: i2c@680 { #address-cells = <1>; #size-cells = <0>; reg = <0x680 0x80>; @@ -1087,7 +1087,7 @@ status = "disabled"; }; - i2c13: i2c-bus@700 { + i2c13: i2c@700 { #address-cells = <1>; #size-cells = <0>; reg = <0x700 0x80>; @@ -1101,7 +1101,7 @@ status = "disabled"; }; - i2c14: i2c-bus@780 { + i2c14: i2c@780 { #address-cells = <1>; #size-cells = <0>; reg = <0x780 0x80>; @@ -1115,7 +1115,7 @@ status = "disabled"; }; - i2c15: i2c-bus@800 { + i2c15: i2c@800 { #address-cells = <1>; #size-cells = <0>; reg = <0x800 0x80>; diff --git a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts index 7fb532f227af..808cd5778e27 100644 --- a/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts +++ b/arch/arm/boot/dts/cirrus/ep7211-edb7211.dts @@ -30,7 +30,7 @@ display-timings { native-mode = <&timing0>; - timing0: 320x240 { + timing0: timing-320x240 { hactive = <320>; hback-porch = <0>; hfront-porch = <0>; diff --git a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts index 2eec5f63d399..2f7c34c649ea 100644 --- a/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts +++ b/arch/arm/boot/dts/intel/ixp/intel-ixp42x-linksys-nslu2.dts @@ -90,11 +90,18 @@ timeout-ms = <5000>; }; - gpio-beeper { - compatible = "gpio-beeper"; + gpio_pwm: pwm { + #pwm-cells = <3>; + compatible = "pwm-gpio"; gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>; }; + beeper { + compatible = "pwm-beeper"; + pwms = <&gpio_pwm 0 1 0>; + beeper-hz = <1000>; + }; + soc { bus@c4000000 { /* The first 16MB region at CS0 on the expansion bus */ diff --git a/arch/arm/boot/dts/marvell/armada-370-xp.dtsi b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi index 0b8c2a64b36f..954c891e5aee 100644 --- a/arch/arm/boot/dts/marvell/armada-370-xp.dtsi +++ b/arch/arm/boot/dts/marvell/armada-370-xp.dtsi @@ -168,7 +168,6 @@ mpic: interrupt-controller@20a00 { compatible = "marvell,mpic"; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; }; diff --git a/arch/arm/boot/dts/marvell/armada-375.dtsi b/arch/arm/boot/dts/marvell/armada-375.dtsi index ddc49547d786..99778b4b7e7b 100644 --- a/arch/arm/boot/dts/marvell/armada-375.dtsi +++ b/arch/arm/boot/dts/marvell/armada-375.dtsi @@ -376,7 +376,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts index 5a9ab8410b7b..2fb7304039be 100644 --- a/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts +++ b/arch/arm/boot/dts/marvell/armada-385-atl-x530.dts @@ -43,6 +43,17 @@ }; }; }; + + led-7seg { + compatible = "gpio-7-segment"; + segment-gpios = <&led_7seg_gpio 0 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 1 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 2 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 3 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 4 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 5 GPIO_ACTIVE_LOW>, + <&led_7seg_gpio 6 GPIO_ACTIVE_LOW>; + }; }; &pciec { @@ -149,7 +160,7 @@ #size-cells = <0>; reg = <3>; - gpio@20 { + led_7seg_gpio: gpio@20 { compatible = "nxp,pca9554"; gpio-controller; #gpio-cells = <2>; diff --git a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts index 7b755bb4e4e7..43202890c959 100644 --- a/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts +++ b/arch/arm/boot/dts/marvell/armada-385-turris-omnia.dts @@ -112,6 +112,19 @@ status = "disabled"; }; + gpio-keys { + compatible = "gpio-keys"; + + front-button { + label = "Front Button"; + linux,code = <KEY_VENDOR>; + linux,can-disable; + gpios = <&mcu 0 12 GPIO_ACTIVE_HIGH>; + /* debouncing is done by the microcontroller */ + debounce-interval = <0>; + }; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "SPDIF"; @@ -218,7 +231,22 @@ #size-cells = <0>; reg = <0>; - /* STM32F0 command interface at address 0x2a */ + mcu: system-controller@2a { + compatible = "cznic,turris-omnia-mcu"; + reg = <0x2a>; + + pinctrl-names = "default"; + pinctrl-0 = <&mcu_pins>; + + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_NONE>; + + gpio-controller; + #gpio-cells = <3>; + + interrupt-controller; + #interrupt-cells = <2>; + }; led-controller@2b { compatible = "cznic,turris-omnia-leds"; @@ -501,6 +529,11 @@ }; &pinctrl { + mcu_pins: mcu-pins { + marvell,pins = "mpp43"; + marvell,function = "gpio"; + }; + pcawan_pins: pcawan-pins { marvell,pins = "mpp46"; marvell,function = "gpio"; diff --git a/arch/arm/boot/dts/marvell/armada-38x.dtsi b/arch/arm/boot/dts/marvell/armada-38x.dtsi index 446861b6b17b..1181b13deabc 100644 --- a/arch/arm/boot/dts/marvell/armada-38x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-38x.dtsi @@ -408,7 +408,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/marvell/armada-39x.dtsi b/arch/arm/boot/dts/marvell/armada-39x.dtsi index 9d1cac49c022..6d05835efb42 100644 --- a/arch/arm/boot/dts/marvell/armada-39x.dtsi +++ b/arch/arm/boot/dts/marvell/armada-39x.dtsi @@ -268,7 +268,6 @@ compatible = "marvell,mpic"; reg = <0x20a00 0x2d0>, <0x21070 0x58>; #interrupt-cells = <1>; - #size-cells = <1>; interrupt-controller; msi-controller; interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts index 07fbfca444d5..36b90c632fd6 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-blackarmor-nas220.dts @@ -35,13 +35,13 @@ gpio_keys { compatible = "gpio-keys"; - reset { + button-reset { label = "Reset"; linux,code = <KEY_POWER>; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - button { + button-power { label = "Power"; linux,code = <KEY_SLEEP>; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; @@ -51,7 +51,7 @@ gpio-leds { compatible = "gpio-leds"; - blue-power { + led-blue-power { label = "nas220:blue:power"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts b/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts index f59ff7578dfc..7e3ee64d4bdf 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-c200-v1.dts @@ -29,25 +29,25 @@ pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; - usb1 { + button-usb1 { label = "USB1 Button"; linux,code = <BTN_0>; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - usb2 { + button-usb2 { label = "USB2 Button"; linux,code = <BTN_1>; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts index 448b0cd23b5f..151edcd140a0 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-cloudbox.dts @@ -58,10 +58,8 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - power { + key-power { label = "Power push button"; linux,code = <KEY_POWER>; gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; @@ -71,11 +69,11 @@ gpio-leds { compatible = "gpio-leds"; - red-fail { + led-red-fail { label = "cloudbox:red:fail"; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; - blue-sata { + led-blue-sata { label = "cloudbox:blue:sata"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-d2net.dts b/arch/arm/boot/dts/marvell/kirkwood-d2net.dts index bd3b266dd766..fcce8730d3e3 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-d2net.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-d2net.dts @@ -37,7 +37,7 @@ gpio-leds { compatible = "gpio-leds"; - red-fail { + led-red-fail { label = "d2net_v2:red:fail"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts index 0c0851cd9bec..2f6793f794cd 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dir665.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dir665.dts @@ -137,38 +137,38 @@ gpio-leds { compatible = "gpio-leds"; - blue-usb { + led-blue-usb { label = "dir665:blue:usb"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - blue-internet { + led-blue-internet { /* Can only be turned on if the Internet * Ethernet port has Link */ label = "dir665:blue:internet"; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; - amber-internet { + led-amber-internet { label = "dir665:amber:internet"; gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; - blue-wifi5g { + led-blue-wifi5g { label = "dir665:blue:5g"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; }; - blue-status { + led-blue-status { label = "dir665:blue:status"; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - blue-wps { + led-blue-wps { label = "dir665:blue:wps"; gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; - amber-status { + led-amber-status { label = "dir665:amber:status"; gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; - blue-24g { + led-blue-24g { label = "dir665:blue:24g"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; @@ -176,15 +176,13 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - reset { + button-reset { label = "reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "wps"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dns320.dts b/arch/arm/boot/dts/marvell/kirkwood-dns320.dts index d6b0f418fd01..d8279e0c4c4f 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dns320.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dns320.dts @@ -24,24 +24,24 @@ &pmx_led_white_usb>; pinctrl-names = "default"; - blue-power { + led-blue-power { label = "dns320:blue:power"; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - blue-usb { + led-blue-usb { label = "dns320:blue:usb"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - orange-l_hdd { + led-orange-l_hdd { label = "dns320:orange:l_hdd"; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - orange-r_hdd { + led-orange-r_hdd { label = "dns320:orange:r_hdd"; gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; - orange-usb { + led-orange-usb { label = "dns320:orange:usb"; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; /* GPIO 35 */ }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dns325.dts b/arch/arm/boot/dts/marvell/kirkwood-dns325.dts index 94d9c06cbbf5..7f396195e977 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dns325.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dns325.dts @@ -24,24 +24,24 @@ &pmx_led_white_usb>; pinctrl-names = "default"; - white-power { + led-white-power { label = "dns325:white:power"; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - white-usb { + led-white-usb { label = "dns325:white:usb"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; /* GPIO 43 */ }; - red-l_hdd { + led-red-l_hdd { label = "dns325:red:l_hdd"; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; }; - red-r_hdd { + led-red-r_hdd { label = "dns325:red:r_hdd"; gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; - red-usb { + led-red-usb { label = "dns325:red:usb"; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi index 0738eb679fcd..20bcd031f3f5 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-dnskw.dtsi @@ -8,23 +8,21 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_power &pmx_button_unmount &pmx_button_reset>; pinctrl-names = "default"; - power { + button-power { label = "Power button"; linux,code = <KEY_POWER>; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; }; - eject { + button-eject { label = "USB unmount button"; linux,code = <KEY_EJECTCD>; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts b/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts index 264938dfa4d9..090f1e2e5bb6 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dockstar.dts @@ -42,12 +42,12 @@ pinctrl-0 = <&pmx_led_green &pmx_led_orange>; pinctrl-names = "default"; - health { + led-health { label = "status:green:health"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - fault { + led-fault { label = "status:orange:fault"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts b/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts index 328516351e84..590bee3c561c 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-dreamplug.dts @@ -85,15 +85,15 @@ &pmx_led_wifi_ap >; pinctrl-names = "default"; - bluetooth { + led-bluetooth { label = "dreamplug:blue:bluetooth"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - wifi { + led-wifi { label = "dreamplug:green:wifi"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; - wifi-ap { + led-wifi-ap { label = "dreamplug:green:wifi_ap"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts b/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts index d4cb3cd3e2a2..d5ac4e3974da 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-goflexnet.dts @@ -85,44 +85,44 @@ >; pinctrl-names = "default"; - health { + led-health { label = "status:green:health"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - fault { + led-fault { label = "status:orange:fault"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - left0 { + led-left0 { label = "status:white:left0"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - left1 { + led-left1 { label = "status:white:left1"; gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; - left2 { + led-left2 { label = "status:white:left2"; gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; - left3 { + led-left3 { label = "status:white:left3"; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - right0 { + led-right0 { label = "status:white:right0"; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; }; - right1 { + led-right1 { label = "status:white:right1"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - right2 { + led-right2 { label = "status:white:right2"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; - right3 { + led-right3 { label = "status:white:right3"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts b/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts index dfb41393941d..d5aa8b505cc0 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-guruplug-server-plus.dts @@ -59,19 +59,19 @@ &pmx_led_wmode_r &pmx_led_wmode_g >; pinctrl-names = "default"; - health-r { + led-health-r { label = "guruplug:red:health"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; - health-g { + led-health-g { label = "guruplug:green:health"; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - wmode-r { + led-wmode-r { label = "guruplug:red:wmode"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; - wmode-g { + led-wmode-g { label = "guruplug:green:wmode"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts index 962a910a6f5c..018c6b8f3e8a 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ib62x0.dts @@ -58,17 +58,15 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_reset &pmx_button_usb_copy>; pinctrl-names = "default"; - copy { + button-copy { label = "USB Copy"; linux,code = <KEY_COPY>; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; @@ -81,16 +79,16 @@ &pmx_led_usb_transfer>; pinctrl-names = "default"; - green-os { + led-green-os { label = "ib62x0:green:os"; gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; - red-os { + led-red-os { label = "ib62x0:red:os"; gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; }; - usb-copy { + led-usb-copy { label = "ib62x0:red:usb_copy"; gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts index aed20185fd7a..91b46e77e0b6 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-iconnect.dts @@ -89,32 +89,32 @@ gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - power-blue { + led-power-blue { label = "power:blue"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; - power-red { + led-power-red { label = "power:red"; gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>; }; - usb1 { + led-usb1 { label = "usb1:blue"; gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; }; - usb2 { + led-usb2 { label = "usb2:blue"; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; }; - usb3 { + led-usb3 { label = "usb3:blue"; gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; - usb4 { + led-usb4 { label = "usb4:blue"; gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; }; - otb { + led-otb { label = "otb:blue"; gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; }; @@ -122,18 +122,16 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = < &pmx_button_reset &pmx_button_otb >; pinctrl-names = "default"; - otb { + button-otb { label = "OTB Button"; linux,code = <KEY_COPY>; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; debounce-interval = <100>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts index 2338f495d517..039362152650 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-iomega_ix2_200.dts @@ -127,44 +127,42 @@ &pmx_led_rebuild &pmx_led_health >; pinctrl-names = "default"; - power_led { + led-power-led { label = "status:white:power_led"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; default-state = "keep"; }; - rebuild_led { + led-rebuild-led { label = "status:white:rebuild_led"; gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; }; - health_led { + led-health-led { label = "status:red:health_led"; gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; }; - backup_led { + led-backup-led { label = "status:blue:backup_led"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; }; gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_reset &pmx_button_power &pmx_button_otb>; pinctrl-names = "default"; - Power { + button-power { label = "Power Button"; linux,code = <KEY_POWER>; gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; }; - Reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; }; - OTB { + button-otb { label = "OTB Button"; linux,code = <KEY_COPY>; gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts index c841eb8e7fb1..974bc9de4702 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-l-50.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-l-50.dts @@ -97,52 +97,52 @@ leds { compatible = "gpio-leds"; - status_green { + led-status-green { label = "l-50:green:status"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - status_red { + led-status-red { label = "l-50:red:status"; gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; }; - wifi { + led-wifi { label = "l-50:green:wifi"; gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; linux,default-trigger = "phy0tpt"; }; - internet_green { + led-internet-green { label = "l-50:green:internet"; gpios = <&gpio2 3 GPIO_ACTIVE_LOW>; }; - internet_red { + led-internet-red { label = "l-50:red:internet"; gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; }; - usb1_green { + led-usb1-green { label = "l-50:green:usb1"; gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; linux,default-trigger = "usbport"; trigger-sources = <&hub_port3>; }; - usb1_red { + led-usb1-red { label = "l-50:red:usb1"; gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; }; - usb2_green { + led-usb2-green { label = "l-50:green:usb2"; gpios = <&gpio2 2 GPIO_ACTIVE_LOW>; linux,default-trigger = "usbport"; trigger-sources = <&hub_port1>; }; - usb2_red { + led-usb2-red { label = "l-50:red:usb2"; gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; }; @@ -193,7 +193,7 @@ keys { compatible = "gpio-keys"; - factory_defaults { + button-factory-defaults { label = "factory_defaults"; gpios = <&gpio0 29 GPIO_ACTIVE_LOW>; linux,code = <KEY_RESTART>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-laplug.dts b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts index 8c2b540eaf4f..90ea6cdee8e0 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-laplug.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-laplug.dts @@ -51,7 +51,7 @@ gpio_keys { compatible = "gpio-keys"; - power { + button-power { label = "Power push button"; linux,code = <KEY_POWER>; gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; @@ -61,11 +61,11 @@ gpio-leds { compatible = "gpio-leds"; - red-fail { + led-red-fail { label = "laplug_v2:red:power"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - blue-power { + led-blue-power { label = "laplug_v2:blue:power"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; linux,default-trigger = "default-on"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi b/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi index b54c9980f636..8a11d2b9d449 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-linkstation.dtsi @@ -88,8 +88,6 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_function &pmx_power_switch &pmx_power_auto_switch>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts index 27fd6e2337d5..8a1c38ab6111 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-linksys-viper.dts @@ -33,18 +33,16 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = < &pmx_btn_wps &pmx_btn_reset >; pinctrl-names = "default"; - wps { + button-wps { label = "WPS Button"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; @@ -56,12 +54,12 @@ pinctrl-0 = < &pmx_led_white_health &pmx_led_white_pulse >; pinctrl-names = "default"; - white-health { + led-white-health { label = "viper:white:health"; gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>; }; - white-pulse { + led-white-pulse { label = "viper:white:pulse"; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi index f80af24b9e90..5e0b139dd4fb 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-lsxl.dtsi @@ -107,24 +107,22 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_function &pmx_power_switch &pmx_power_auto_switch>; pinctrl-names = "default"; - option { + button-option { label = "Function Button"; linux,code = <KEY_OPTION>; gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; - reserved { + button-reserved { label = "Power-on Switch"; linux,code = <KEY_RESERVED>; linux,input-type = <5>; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; - power { + button-power { label = "Power-auto Switch"; linux,code = <KEY_ESC>; linux,input-type = <5>; @@ -139,28 +137,28 @@ &pmx_led_function_blue>; pinctrl-names = "default"; - func_blue { + led-func-blue { label = "lsxl:blue:func"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; - alarm { + led-alarm { label = "lsxl:red:alarm"; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; - info { + led-info { label = "lsxl:amber:info"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - power { + led-power { label = "lsxl:blue:power"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - func_red { + led-func-red { label = "lsxl:red:func"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts b/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts index e87ea7146546..6533b49a15b2 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-mplcec4.dts @@ -114,36 +114,36 @@ >; pinctrl-names = "default"; - health { + led-health { label = "status:green:health"; gpios = <&gpio0 7 GPIO_ACTIVE_LOW>; }; - user1o { + led-user1o { label = "user1:orange"; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; default-state = "on"; }; - user1g { + led-user1g { label = "user1:green"; gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; default-state = "on"; }; - user0o { + led-user0o { label = "user0:orange"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; default-state = "on"; }; - user0g { + led-user0g { label = "user0:green"; gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; default-state = "on"; }; - misc { + led-misc { label = "status:orange:misc"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; default-state = "on"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts index 5a77286136c7..e3b41784c876 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-mv88f6281gtw-ge.dts @@ -73,17 +73,17 @@ pinctrl-0 = <&pmx_leds &pmx_usb_led>; pinctrl-names = "default"; - green-status { + led-green-status { label = "gtw:green:Status"; gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; }; - red-status { + led-red-status { label = "gtw:red:Status"; gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "gtw:green:USB"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; @@ -91,17 +91,15 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_keys>; pinctrl-names = "default"; - restart { + button-restart { label = "SWR Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; }; - wps { + button-wps { label = "WPS Button"; linux,code = <KEY_WPS_BUTTON>; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi index b5737026e244..d4edf2727388 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-netxbig.dtsi @@ -53,26 +53,24 @@ gpio-keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; /* * esc and power represent a three position rocker * switch. Thus the conventional KEY_POWER does not fit */ - exc { + button-exc { label = "Back power switch (on|auto)"; linux,code = <KEY_ESC>; linux,input-type = <5>; gpios = <&gpio0 13 GPIO_ACTIVE_LOW>; }; - power { + button-power { label = "Back power switch (auto|off)"; linux,code = <KEY_1>; linux,input-type = <5>; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; - option { + button-option { label = "Function button"; linux,code = <KEY_OPTION>; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi index 51530ea86622..d6b615cf6390 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2-common.dtsi @@ -55,10 +55,8 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; - power { + button-power { label = "Power push button"; linux,code = <KEY_POWER>; gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>; @@ -68,7 +66,7 @@ gpio-leds { compatible = "gpio-leds"; - red-fail { + led-red-fail { label = "ns2:red:fail"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts b/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts index b0cb5907ed63..686bcd6f0f3c 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ns2lite.dts @@ -24,7 +24,7 @@ gpio-leds { compatible = "gpio-leds"; - blue-sata { + led-blue-sata { label = "ns2:blue:sata"; gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; linux,default-trigger = "disk-activity"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts index c1799a07816e..3555ac1c3b15 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310.dts @@ -87,43 +87,43 @@ &pmx_led_hdd_green &pmx_led_hdd_red>; pinctrl-names = "default"; - green-sys { + led-green-sys { label = "nsa310:green:sys"; gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; - red-sys { + led-red-sys { label = "nsa310:red:sys"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - green-hdd { + led-green-hdd { label = "nsa310:green:hdd"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; - red-hdd { + led-red-hdd { label = "nsa310:red:hdd"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - green-esata { + led-green-esata { label = "nsa310:green:esata"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - red-esata { + led-red-esata { label = "nsa310:red:esata"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "nsa310:green:usb"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - red-usb { + led-red-usb { label = "nsa310:red:usb"; gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; }; - green-copy { + led-green-copy { label = "nsa310:green:copy"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - red-copy { + led-red-copy { label = "nsa310:red:copy"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts index b85e314f045a..ddf84092aade 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310a.dts @@ -75,39 +75,39 @@ gpio-leds { compatible = "gpio-leds"; - green-sys { + led-green-sys { label = "nsa310:green:sys"; gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; - red-sys { + led-red-sys { label = "nsa310:red:sys"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - green-hdd { + led-green-hdd { label = "nsa310:green:hdd"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; - red-hdd { + led-red-hdd { label = "nsa310:red:hdd"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - green-esata { + led-green-esata { label = "nsa310:green:esata"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - red-esata { + led-red-esata { label = "nsa310:red:esata"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "nsa310:green:usb"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - green-copy { + led-green-copy { label = "nsa310:green:copy"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - red-copy { + led-red-copy { label = "nsa310:red:copy"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts index 49da633a1bc0..47deb93c90a5 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa310s.dts @@ -35,24 +35,22 @@ keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = <KEY_POWER>; gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>; }; - copy { + button-copy { label = "Copy Button"; linux,code = <KEY_COPY>; gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts index 652405e65006..dd5c8ffc8781 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa320.dts @@ -142,39 +142,39 @@ &pmx_led_hdd1_green &pmx_led_hdd1_red>; pinctrl-names = "default"; - green-sys { + led-green-sys { label = "nsa320:green:sys"; gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; - orange-sys { + led-orange-sys { label = "nsa320:orange:sys"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - green-hdd1 { + led-green-hdd1 { label = "nsa320:green:hdd1"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; - red-hdd1 { + led-red-hdd1 { label = "nsa320:red:hdd1"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - green-hdd2 { + led-green-hdd2 { label = "nsa320:green:hdd2"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - red-hdd2 { + led-red-hdd2 { label = "nsa320:red:hdd2"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "nsa320:green:usb"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - green-copy { + led-green-copy { label = "nsa320:green:copy"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - red-copy { + led-red-copy { label = "nsa320:red:copy"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts b/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts index 371456de34b2..f0786a5f2ce6 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa325.dts @@ -162,39 +162,39 @@ &pmx_led_hdd1_green &pmx_led_hdd1_red>; pinctrl-names = "default"; - green-sys { + led-green-sys { label = "nsa325:green:sys"; gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>; }; - orange-sys { + led-orange-sys { label = "nsa325:orange:sys"; gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>; }; - green-hdd1 { + led-green-hdd1 { label = "nsa325:green:hdd1"; gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>; }; - red-hdd1 { + led-red-hdd1 { label = "nsa325:red:hdd1"; gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; }; - green-hdd2 { + led-green-hdd2 { label = "nsa325:green:hdd2"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; }; - red-hdd2 { + led-red-hdd2 { label = "nsa325:red:hdd2"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; }; - green-usb { + led-green-usb { label = "nsa325:green:usb"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; }; - green-copy { + led-green-copy { label = "nsa325:green:copy"; gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; }; - red-copy { + led-red-copy { label = "nsa325:red:copy"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi index ea3d36512e9f..e9bd9c551af5 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-nsa3x0-common.dtsi @@ -63,22 +63,20 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_btn_reset &pmx_btn_copy &pmx_btn_power>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>; }; - copy { + button-copy { label = "Copy Button"; linux,code = <KEY_COPY>; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts index 8ea430168ea5..20c6290d2037 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a6.dts @@ -115,10 +115,8 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_gpio_init>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - power { + button-power { label = "Init Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts index 946f0f453dd1..9c438f10f737 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-openblocks_a7.dts @@ -136,8 +136,6 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_gpio_init>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; button { label = "Init Button"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts b/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts index f9e95e55f36d..39a5345332da 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-pogo_e02.dts @@ -33,12 +33,12 @@ gpio-leds { compatible = "gpio-leds"; - health { + led-health { label = "pogo_e02:green:health"; gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - fault { + led-fault { label = "pogo_e02:orange:fault"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts index 5aa4669ae254..0e9c4cf79822 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-pogoplug-series-4.dts @@ -29,12 +29,10 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_eject>; pinctrl-names = "default"; - eject { + button-eject { debounce-interval = <50>; wakeup-source; linux,code = <KEY_EJECTCD>; @@ -48,12 +46,12 @@ pinctrl-0 = <&pmx_led_green &pmx_led_red>; pinctrl-names = "default"; - health { + led-health { label = "pogoplugv4:green:health"; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; default-state = "on"; }; - fault { + led-fault { label = "pogoplugv4:red:fault"; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts index ae8f493c9a0f..eb185273376e 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug-esata.dts @@ -33,7 +33,7 @@ pinctrl-0 = <&pmx_led_blue>; pinctrl-names = "default"; - health { + led-health { label = "sheevaplug:blue:health"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts index c73cc904e5c4..ce73fcf2255f 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-sheevaplug.dts @@ -28,13 +28,13 @@ pinctrl-0 = <&pmx_led_blue &pmx_led_red>; pinctrl-names = "default"; - health { + led-health { label = "sheevaplug:blue:health"; gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; default-state = "keep"; }; - misc { + led-misc { label = "sheevaplug:red:misc"; gpios = <&gpio1 14 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi b/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi index 20964eb48fd7..6b7c5218b1fb 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-synology.dtsi @@ -410,7 +410,7 @@ pinctrl-0 = <&pmx_alarmled_12>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:alarm"; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; @@ -424,42 +424,42 @@ &pmx_hddled_26 &pmx_hddled_27>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; - hdd2-green { + led-hdd2-green { label = "synology:green:hdd2"; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; }; - hdd2-amber { + led-hdd2-amber { label = "synology:amber:hdd2"; gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; - hdd3-green { + led-hdd3-green { label = "synology:green:hdd3"; gpios = <&gpio0 24 GPIO_ACTIVE_LOW>; }; - hdd3-amber { + led-hdd3-amber { label = "synology:amber:hdd3"; gpios = <&gpio0 25 GPIO_ACTIVE_LOW>; }; - hdd4-green { + led-hdd4-green { label = "synology:green:hdd4"; gpios = <&gpio0 26 GPIO_ACTIVE_LOW>; }; - hdd4-amber { + led-hdd4-amber { label = "synology:amber:hdd4"; gpios = <&gpio0 27 GPIO_ACTIVE_LOW>; }; @@ -471,12 +471,12 @@ pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; @@ -488,22 +488,22 @@ pinctrl-0 = <&pmx_hddled_21 &pmx_hddled_23 &pmx_hddled_20 &pmx_hddled_22>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio0 21 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio0 23 GPIO_ACTIVE_LOW>; }; - hdd2-green { + led-hdd2-green { label = "synology:green:hdd2"; gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; }; - hdd2-amber { + led-hdd2-amber { label = "synology:amber:hdd2"; gpios = <&gpio0 22 GPIO_ACTIVE_LOW>; }; @@ -518,52 +518,52 @@ &pmx_hddled_45>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; - hdd2-green { + led-hdd2-green { label = "synology:green:hdd2"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - hdd2-amber { + led-hdd2-amber { label = "synology:amber:hdd2"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; }; - hdd3-green { + led-hdd3-green { label = "synology:green:hdd3"; gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; }; - hdd3-amber { + led-hdd3-amber { label = "synology:amber:hdd3"; gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; }; - hdd4-green { + led-hdd4-green { label = "synology:green:hdd4"; gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; }; - hdd4-amber { + led-hdd4-amber { label = "synology:amber:hdd4"; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - hdd5-green { + led-hdd5-green { label = "synology:green:hdd5"; gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; }; - hdd5-amber { + led-hdd5-amber { label = "synology:amber:hdd5"; gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; }; @@ -575,22 +575,22 @@ pinctrl-0 = <&pmx_hddled_38 &pmx_hddled_39 &pmx_hddled_36 &pmx_hddled_37>; pinctrl-names = "default"; - hdd1-green { + led-hdd1-green { label = "synology:green:hdd1"; gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; }; - hdd1-amber { + led-hdd1-amber { label = "synology:amber:hdd1"; gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; }; - hdd2-green { + led-hdd2-green { label = "synology:green:hdd2"; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; }; - hdd2-amber { + led-hdd2-amber { label = "synology:amber:hdd2"; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/kirkwood-t5325.dts b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts index ad093324e075..a6e77a487d00 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-t5325.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-t5325.dts @@ -156,12 +156,10 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_button_power>; pinctrl-names = "default"; - power { + button-power { label = "Power Button"; linux,code = <KEY_POWER>; gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts index 30892c19aceb..a2e0ad4b84d8 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219-6281.dts @@ -35,17 +35,15 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - copy { + button-copy { label = "USB Copy"; linux,code = <KEY_COPY>; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts index aba1205981f1..35be6bce1dba 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts +++ b/arch/arm/boot/dts/marvell/kirkwood-ts219-6282.dts @@ -35,17 +35,15 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - copy { + button-copy { label = "USB Copy"; linux,code = <KEY_COPY>; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi index 717236853e45..f136059607b7 100644 --- a/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi +++ b/arch/arm/boot/dts/marvell/kirkwood-ts419.dtsi @@ -36,17 +36,15 @@ gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_reset_button &pmx_USB_copy_button>; pinctrl-names = "default"; - copy { + button-copy { label = "USB Copy"; linux,code = <KEY_COPY>; gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; }; - reset { + button-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi b/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi index c2d87ba6190a..055ac754c5fd 100644 --- a/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi +++ b/arch/arm/boot/dts/marvell/mvebu-linkstation-gpio-simple.dtsi @@ -48,8 +48,6 @@ / { gpio_keys { compatible = "gpio-keys"; - #address-cells = <1>; - #size-cells = <0>; pinctrl-0 = <&pmx_power_switch>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts index 03471d30bfd9..12a4aac2633e 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-d2-network.dts @@ -35,22 +35,21 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - front_button { + + button-front { label = "Front Push Button"; linux,code = <KEY_POWER>; gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; }; - power_rocker_sw_on { + switch-power-rocker-sw-on { label = "Power rocker switch (on|auto)"; linux,input-type = <5>; /* EV_SW */ linux,code = <1>; /* D2NET_SWITCH_POWER_ON */ gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; }; - power_rocker_sw_off { + switch-power-rocker-sw-off { label = "Power rocker switch (auto|off)"; linux,input-type = <5>; /* EV_SW */ linux,code = <2>; /* D2NET_SWITCH_POWER_OFF */ diff --git a/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts index f17e25ac98dd..f81acb9b7223 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lacie-ethernet-disk-mini-v2.dts @@ -39,9 +39,8 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_power_button>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - button@1 { + + button-1 { label = "Power-on Switch"; linux,code = <KEY_POWER>; gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; @@ -53,7 +52,7 @@ pinctrl-0 = <&pmx_power_led>; pinctrl-names = "default"; - led@1 { + led-1 { label = "power:blue"; gpios = <&gpio0 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts index ee751995c8d0..79fee048c900 100644 --- a/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts +++ b/arch/arm/boot/dts/marvell/orion5x-linkstation-lschl.dts @@ -61,7 +61,7 @@ }; gpio_keys { - func { + func-button { label = "Function Button"; linux,code = <KEY_OPTION>; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; @@ -90,7 +90,7 @@ gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; }; - func { + func-led { label = "lschl:func:blue:top"; gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts index 2fbc17d6dfa4..e0da406c430f 100644 --- a/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts +++ b/arch/arm/boot/dts/marvell/orion5x-lswsgl.dts @@ -74,22 +74,21 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - func { + + key-func { label = "Function Button"; linux,code = <KEY_OPTION>; gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; }; - power { + key-power { label = "Power-on Switch"; linux,input-type = <5>; /* EV_SW */ linux,code = <KEY_RESERVED>; /* LSMINI_SW_POWER */ gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; }; - autopower { + key-autopower { label = "Power-auto Switch"; linux,input-type = <5>; /* EV_SW */ linux,code = <KEY_ESC>; /* LSMINI_SW_AUTOPOWER */ @@ -103,24 +102,24 @@ &pmx_led_power>; pinctrl-names = "default"; - alarm { + led-alarm { label = "lswsgl:alarm:red"; - gpio = <&gpio0 2 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; }; - info { + led-info { label = "lswsgl:info:amber"; - gpio = <&gpio0 3 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; }; - func { + led-func { label = "lswsgl:func:blue:top"; - gpio = <&gpio0 9 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; }; - power { + led-power { label = "lswsgl:power:blue:bottom"; - gpio = <&gpio0 14 GPIO_ACTIVE_LOW>; + gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; default-state = "on"; }; }; diff --git a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts index d57859998350..cb1bd24b7ae3 100644 --- a/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts +++ b/arch/arm/boot/dts/marvell/orion5x-maxtor-shared-storage-2.dts @@ -35,15 +35,14 @@ compatible = "gpio-keys"; pinctrl-0 = <&pmx_buttons>; pinctrl-names = "default"; - #address-cells = <1>; - #size-cells = <0>; - power { + + key-power { label = "Power"; linux,code = <KEY_POWER>; gpios = <&gpio0 11 GPIO_ACTIVE_LOW>; }; - reset { + key-reset { label = "Reset"; linux,code = <KEY_RESTART>; gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts b/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts index fb203e7d37f5..d63ea15539aa 100644 --- a/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts +++ b/arch/arm/boot/dts/marvell/orion5x-netgear-wnr854t.dts @@ -35,7 +35,7 @@ pinctrl-0 = <&pmx_reset_button>; pinctrl-names = "default"; - reset { + key-reset { label = "Reset Button"; linux,code = <KEY_RESTART>; gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; diff --git a/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts b/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts index fd78aa02a3c5..75ab913b21e5 100644 --- a/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts +++ b/arch/arm/boot/dts/marvell/orion5x-rd88f5182-nas.dts @@ -32,7 +32,7 @@ pinctrl-0 = <&pmx_debug_led>; pinctrl-names = "default"; - led@0 { + led-0 { label = "rd88f5182:cpu"; linux,default-trigger = "heartbeat"; gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; diff --git a/arch/arm/boot/dts/mediatek/mt2701-evb.dts b/arch/arm/boot/dts/mediatek/mt2701-evb.dts index 9c7325f18933..4c76366aa938 100644 --- a/arch/arm/boot/dts/mediatek/mt2701-evb.dts +++ b/arch/arm/boot/dts/mediatek/mt2701-evb.dts @@ -231,7 +231,7 @@ <MT2701_PIN_238_EXT_SDIO1__FUNC_EXT_SDIO1>, <MT2701_PIN_237_EXT_SDIO2__FUNC_EXT_SDIO2>, <MT2701_PIN_236_EXT_SDIO3__FUNC_EXT_SDIO3>; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up; }; }; diff --git a/arch/arm/boot/dts/mediatek/mt7623.dtsi b/arch/arm/boot/dts/mediatek/mt7623.dtsi index f0b4a09004b3..814586abc297 100644 --- a/arch/arm/boot/dts/mediatek/mt7623.dtsi +++ b/arch/arm/boot/dts/mediatek/mt7623.dtsi @@ -1143,13 +1143,13 @@ <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>, <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>; input-enable; - drive-strength = <MTK_DRIVE_2mA>; + drive-strength = <2>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; pins-clk { pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>; - drive-strength = <MTK_DRIVE_2mA>; + drive-strength = <2>; bias-pull-down = <MTK_PUPD_SET_R1R0_01>; }; @@ -1167,14 +1167,14 @@ <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; input-enable; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; pins-clk { pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; bias-pull-down; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; }; pins-wp { @@ -1197,13 +1197,13 @@ <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>, <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>; input-enable; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; pins-clk { pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; }; @@ -1211,7 +1211,7 @@ nand_pins_default: nanddefault { pins-ale { pinmux = <MT7623_PIN_116_MSDC0_CMD_FUNC_NALE>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -1226,13 +1226,13 @@ <MT7623_PIN_115_MSDC0_RSTB_FUNC_NLD8>, <MT7623_PIN_119_MSDC0_DAT2_FUNC_NLD2>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up; }; pins-we { pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_NWEB>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; }; diff --git a/arch/arm/boot/dts/nspire/nspire-classic.dtsi b/arch/arm/boot/dts/nspire/nspire-classic.dtsi index a6e9cbf51524..0ee53d3ecd54 100644 --- a/arch/arm/boot/dts/nspire/nspire-classic.dtsi +++ b/arch/arm/boot/dts/nspire/nspire-classic.dtsi @@ -55,7 +55,7 @@ }; / { - memory { + memory@10000000 { device_type = "memory"; reg = <0x10000000 0x2000000>; /* 32 MB */ }; diff --git a/arch/arm/boot/dts/nspire/nspire-cx.dts b/arch/arm/boot/dts/nspire/nspire-cx.dts index 29f0181e5b38..debeff0ec010 100644 --- a/arch/arm/boot/dts/nspire/nspire-cx.dts +++ b/arch/arm/boot/dts/nspire/nspire-cx.dts @@ -122,7 +122,7 @@ model = "TI-NSPIRE CX"; compatible = "ti,nspire-cx"; - memory { + memory@10000000 { device_type = "memory"; reg = <0x10000000 0x4000000>; /* 64 MB */ }; diff --git a/arch/arm/boot/dts/nspire/nspire.dtsi b/arch/arm/boot/dts/nspire/nspire.dtsi index d56fef7250db..95588b716c6f 100644 --- a/arch/arm/boot/dts/nspire/nspire.dtsi +++ b/arch/arm/boot/dts/nspire/nspire.dtsi @@ -170,9 +170,12 @@ }; watchdog: watchdog@90060000 { - compatible = "arm,primecell"; + compatible = "arm,sp805", "arm,primecell"; reg = <0x90060000 0x1000>; interrupts = <3>; + clocks = <&apb_pclk>, <&apb_pclk>; + clock-names = "wdog_clk", "apb_pclk"; + status = "disabled"; }; rtc: rtc@90090000 { diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts index 5787ae95d3b4..1f07ba382910 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm730-kudo.dts @@ -525,7 +525,7 @@ }; }; - i2c-bus@4 { + i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; @@ -537,7 +537,7 @@ }; }; - i2c-bus@5 { + i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; @@ -549,7 +549,7 @@ }; }; - i2c-bus@6 { + i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; @@ -561,7 +561,7 @@ }; }; - i2c-bus@7 { + i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; @@ -580,7 +580,7 @@ reg = <0x77>; i2c-mux-idle-disconnect; - i2c-bus@2 { + i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; @@ -620,7 +620,7 @@ reg = <0x77>; i2c-mux-idle-disconnect; - i2c-bus@0 { + i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; @@ -632,7 +632,7 @@ }; }; - i2c-bus@1 { + i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; @@ -691,7 +691,7 @@ reg = <0x77>; i2c-mux-idle-disconnect; - i2c-bus@3 { + i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; @@ -703,7 +703,7 @@ }; }; - i2c-bus@4 { + i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; @@ -715,7 +715,7 @@ }; }; - i2c-bus@5 { + i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; @@ -726,7 +726,7 @@ reg = <0x28>; }; }; - i2c-bus@6 { + i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; diff --git a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts index baa39d0c1032..087f4ac43187 100644 --- a/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts +++ b/arch/arm/boot/dts/nuvoton/nuvoton-npcm750-runbmc-olympus.dts @@ -215,43 +215,43 @@ reg = <0x70>; i2c-mux-idle-disconnect; - i2c_slot1a: i2c-bus@0 { + i2c_slot1a: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; - i2c_slot1b: i2c-bus@1 { + i2c_slot1b: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; }; - i2c_slot2a: i2c-bus@2 { + i2c_slot2a: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; }; - i2c_slot2b: i2c-bus@3 { + i2c_slot2b: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; - i2c_slot3: i2c-bus@4 { + i2c_slot3: i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; - i2c_slot4: i2c-bus@5 { + i2c_slot4: i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; - i2c_slot5: i2c-bus@6 { + i2c_slot5: i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; @@ -265,24 +265,24 @@ #size-cells = <0>; i2c-mux-idle-disconnect; - i2c_m2_s1: i2c-bus@0 { + i2c_m2_s1: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; - i2c_m2_s2: i2c-bus@1 { + i2c_m2_s2: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; }; - i2c_m2_s3: i2c-bus@2 { + i2c_m2_s3: i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; }; - i2c_m2_s4: i2c-bus@3 { + i2c_m2_s4: i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 231c0d73a53e..92e291603ea1 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -99,6 +99,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6dl-icore.dtb \ imx6dl-icore-mipi.dtb \ imx6dl-icore-rqs.dtb \ + imx6dl-kontron-samx6i-ads2.dtb \ imx6dl-lanmcu.dtb \ imx6dl-mamoj.dtb \ imx6dl-mba6a.dtb \ @@ -207,6 +208,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ imx6q-icore-ofcap10.dtb \ imx6q-icore-ofcap12.dtb \ imx6q-icore-rqs.dtb \ + imx6q-kontron-samx6i-ads2.dtb \ imx6q-kp-tpc.dtb \ imx6q-logicpd.dtb \ imx6q-marsboard.dtb \ diff --git a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi index 13756d39fb7b..0029c12f16c8 100644 --- a/arch/arm/boot/dts/nxp/imx/e60k02.dtsi +++ b/arch/arm/boot/dts/nxp/imx/e60k02.dtsi @@ -14,6 +14,10 @@ #include <dt-bindings/input/input.h> / { + aliases { + mmc0 = &usdhc2; + mmc1 = &usdhc3; + }; chosen { stdout-path = &uart1; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts index b61d55ca1467..de6b7607510a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-apf51dev.dts @@ -25,8 +25,8 @@ pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { - lw700 { - native-mode; + native-mode = <&timing0>; + timing0: timing-lw700 { clock-frequency = <33000033>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts index 16ff543f3fbf..f4a47e8348b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts @@ -89,7 +89,7 @@ status = "disabled"; display-timings { native-mode = <&timing1>; - timing1: claawvga { + timing1: timing-claawvga { clock-frequency = <27000000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts index 2bd0761c7e90..079bd3d14999 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts @@ -58,8 +58,8 @@ pinctrl-0 = <&pinctrl_lcd>; display-timings { - 800x480p60 { - native-mode; + native-mode = <&timing0>; + timing0: timing-800x480p60 { clock-frequency = <30066000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts index 1353d985969c..ba0c62994f75 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53evk.dts @@ -17,8 +17,8 @@ pinctrl-0 = <&pinctrl_ipu_disp1>; display-timings { - 800x480p60 { - native-mode; + native-mode = <&timing0>; + timing0: timing-800x480p60 { clock-frequency = <31500000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts index 4d77b6077fc1..558751e730f3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts @@ -64,6 +64,7 @@ reg = <0>; lvds_decoder_in: endpoint { + data-mapping = "jeida-18"; remote-endpoint = <&lvds0_out>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts index a7f77527269d..a02d77bb5672 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts @@ -67,7 +67,7 @@ }; display-timings { - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -83,7 +83,7 @@ pixelclk-active = <0>; }; - ETV570 { + timing-etc570 { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -99,7 +99,7 @@ pixelclk-active = <0>; }; - ET0350 { + timing-et0350 { clock-frequency = <6413760>; hactive = <320>; vactive = <240>; @@ -115,7 +115,7 @@ pixelclk-active = <0>; }; - ET0430 { + timing-et0430 { clock-frequency = <9009000>; hactive = <480>; vactive = <272>; @@ -131,7 +131,7 @@ pixelclk-active = <1>; }; - ET0500 { + timing-et0500 { clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -147,7 +147,7 @@ pixelclk-active = <0>; }; - ET0700 { /* same as ET0500 */ + timing-et0700 { /* same as ET0500 */ clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -163,7 +163,7 @@ pixelclk-active = <0>; }; - ETQ570 { + timing-etq570 { clock-frequency = <6596040>; hactive = <320>; vactive = <240>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts index 6cdf2082c742..e10c179dbdb3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x13x.dts @@ -191,7 +191,7 @@ display-timings { native-mode = <&lvds0_timing0>; - lvds0_timing0: hsd100pxn1 { + lvds0_timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; @@ -207,7 +207,7 @@ pixelclk-active = <1>; }; - lvds0_timing1: nl12880bc20 { + lvds0_timing1: timing-nl12880bc20 { clock-frequency = <71000000>; hactive = <1280>; vactive = <800>; @@ -233,7 +233,7 @@ display-timings { native-mode = <&lvds1_timing0>; - lvds1_timing0: hsd100pxn1 { + lvds1_timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts index dfa6f64d43cc..c9b2ea2b24b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos2_4.dts @@ -82,11 +82,10 @@ compatible = "lg,lg4573"; spi-max-frequency = <10000000>; reg = <0>; - power-on-delay = <10>; display-timings { - 480x800p57 { - native-mode; + native-mode = <&timing0>; + timing0: timing-480x800p57 { clock-frequency = <27000027>; hactive = <480>; vactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts index a5ac79346854..9ec038f1d0ff 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_4.dts @@ -36,8 +36,8 @@ status = "okay"; display-timings { - 480x800p60 { - native-mode; + native-mode = <&timing0>; + timing0: timing-480x800p60 { clock-frequency = <30000000>; hactive = <480>; vactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts index 5a25bdbbeb68..b3129832f471 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-aristainetos_7.dts @@ -25,8 +25,8 @@ status = "okay"; display-timings { - 800x480p60 { - native-mode; + native-mode = <&timing0>; + timing0: timing-800x480p60 { clock-frequency = <33246000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts new file mode 100644 index 000000000000..6a0c53f23a15 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i-ads2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 + +/dts-v1/; + +#include "imx6dl.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" +#include "imx6qdl-kontron-samx6i-ads2.dtsi" + +/ { + model = "Kontron SMARC-sAMX6i Dual-Lite/Solo on SMARC Eval 2.0 carrier"; + compatible = "kontron,imx6dl-samx6i-ads2", "kontron,imx6dl-samx6i", "fsl,imx6dl"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi index a864fdbd5f16..5a9b819d7ee8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-kontron-samx6i.dtsi @@ -7,6 +7,6 @@ #include "imx6qdl-kontron-samx6i.dtsi" / { - model = "Kontron SMARC sAMX6i Dual-Lite/Solo"; + model = "Kontron SMARC-sAMX6i Dual-Lite/Solo"; compatible = "kontron,imx6dl-samx6i", "fsl,imx6dl"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts new file mode 100644 index 000000000000..94c395cc020e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i-ads2.dts @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0 OR X11 + +/dts-v1/; + +#include "imx6q.dtsi" +#include "imx6qdl-kontron-samx6i.dtsi" +#include "imx6qdl-kontron-samx6i-ads2.dtsi" + +/ { + model = "Kontron SMARC-sAMX6i Quad/Dual on SMARC Eval 2.0 carrier"; + compatible = "kontron,imx6q-samx6i-ads2", "kontron,imx6q-samx6i", "fsl,imx6q"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi index ff062f4fd726..e76963436079 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-kontron-samx6i.dtsi @@ -7,6 +7,6 @@ #include "imx6qdl-kontron-samx6i.dtsi" / { - model = "Kontron SMARC sAMX6i Quad/Dual"; + model = "Kontron SMARC-sAMX6i Quad/Dual"; compatible = "kontron,imx6q-samx6i", "fsl,imx6q"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi index 48ffb3ee01bd..082a2e3a391f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw52xx.dtsi @@ -485,7 +485,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi index 1eae438fbdae..8ec442038ea0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw53xx.dtsi @@ -482,7 +482,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi index c2ec8572c8a5..9df9f79affae 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw54xx.dtsi @@ -529,7 +529,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi index 7cee983da669..7693f92195d5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw560x.dtsi @@ -584,7 +584,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi index fbc704c064b6..9d0836df0fed 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5903.dtsi @@ -486,7 +486,7 @@ display-timings { native-mode = <&timing0>; - timing0: g101evn010 { + timing0: timing-g101evn010 { clock-frequency = <68930000>; hactive = <1280>; vactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi index 070506279186..f4cb9e1d34a9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw5904.dtsi @@ -551,7 +551,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi new file mode 100644 index 000000000000..b4a79245b7b6 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i-ads2.dtsi @@ -0,0 +1,148 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree include for the Kontron SMARC-sAMX6i board on a SMARC Eval + * 2.0 carrier (ADS2). + * + */ + +/ { + chosen { + stdout-path = "serial0:115200n8"; + }; + + sound { + #address-cells = <1>; + #size-cells = <0>; + compatible = "simple-audio-card"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,widgets = + "Headphone", "Headphone Jack", + "Line", "Line Out Jack", + "Microphone", "Microphone Jack", + "Line", "Line In Jack"; + simple-audio-card,routing = + "Line Out Jack", "LINEOUTR", + "Line Out Jack", "LINEOUTL", + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "IN1L", "Line In Jack", + "IN1R", "Line In Jack", + "Microphone Jack", "MICBIAS", + "IN2L", "Microphone Jack", + "IN2R", "Microphone Jack"; + + simple-audio-card,cpu { + sound-dai = <&ssi1>; + }; + + dailink_master: simple-audio-card,codec { + sound-dai = <&wm8904>; + }; + }; + + reg_codec_mic: regulator-codec-mic { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MIC"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + reg_codec_1p8v: regulator-codec-1p8v { + compatible = "regulator-fixed"; + regulator-name = "V_1V8_S0_CODEC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; +}; + +&audmux { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&can2 { + status = "okay"; +}; + +&ecspi4 { + flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <100000000>; + m25p,fast-read; + }; +}; + +&fec { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + wm8904: audio-codec@1a { + compatible = "wlf,wm8904"; + reg = <0x1a>; + #sound-dai-cells = <0>; + clocks = <&clks IMX6QDL_CLK_CKO2>; + clock-names = "mclk"; + AVDD-supply = <®_codec_1p8v>; + CPVDD-supply = <®_codec_1p8v>; + DBVDD-supply = <®_codec_1p8v>; + DCVDD-supply = <®_codec_1p8v>; + MICVDD-supply = <®_codec_mic>; + }; +}; + +&i2c3 { + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&pcie { + status = "okay"; +}; + +&ssi1 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&usbh1 { + status = "okay"; +}; + +&usbotg { + status = "okay"; +}; + +&usdhc3 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi index 668d33d1ff0c..99b5e78458aa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-kontron-samx6i.dtsi @@ -61,6 +61,18 @@ vin-supply = <®_smarc_suppy>; }; + reg_sdio: regulator-sdio { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_sdio>; + regulator-name = "V_3V3_SD"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + }; + reg_smarc_lcdbklt: regulator-smarc-lcdbklt { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -137,7 +149,7 @@ status = "disabled"; }; - i2c_intern: i2c-gpio-intern { + i2c_intern: i2c-0 { compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_gpio_intern>; @@ -148,7 +160,7 @@ #size-cells = <0>; }; - i2c_lcd: i2c-gpio-lcd { + i2c_lcd: i2c-1 { compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_gpio_lcd>; @@ -160,7 +172,7 @@ status = "disabled"; }; - i2c_cam: i2c-gpio-cam { + i2c_cam: i2c-2 { compatible = "i2c-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_gpio_cam>; @@ -178,7 +190,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; - audmux_ssi1 { + mux-ssi1 { fsl,audmux-port = <MX51_AUDMUX_PORT1_SSI0>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT3) | @@ -190,7 +202,7 @@ >; }; - audmux_adu3 { + mux-aud3 { fsl,audmux-port = <MX51_AUDMUX_PORT3>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN @@ -198,7 +210,7 @@ >; }; - audmux_ssi2 { + mux-ssi2 { fsl,audmux-port = <MX51_AUDMUX_PORT2_SSI1>; fsl,port-config = < (IMX_AUDMUX_V2_PTCR_TFSEL(MX51_AUDMUX_PORT4) | @@ -210,7 +222,7 @@ >; }; - audmux_adu4 { + mux-aud4 { fsl,audmux-port = <MX51_AUDMUX_PORT4>; fsl,port-config = < IMX_AUDMUX_V2_PTCR_SYN @@ -357,10 +369,6 @@ regulator-always-on; }; - /* - * Per schematics, of all VGEN's, only VGEN5 has some - * usage ... but even that - over DNI resistor - */ vgen1 { regulator-min-microvolt = <800000>; regulator-max-microvolt = <1550000>; @@ -381,8 +389,7 @@ regulator-max-microvolt = <3300000>; }; - reg_2p5v_s0: vgen5 { - regulator-name = "V_2V5_S0"; + vgen5 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; }; @@ -645,6 +652,12 @@ >; }; + pinctrl_reg_sdio: reg-sdiogrp { + fsl,pins = < + MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* SDIO_PWR_EN */ + >; + }; + pinctrl_uart1: uart1grp { fsl,pins = < MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 @@ -697,7 +710,6 @@ MX6QDL_PAD_NANDF_CS1__GPIO6_IO14 0x1b0b0 /* CD */ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b0 /* WP */ - MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PWR_EN */ >; }; @@ -731,7 +743,6 @@ &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; - wake-up-gpio = <&gpio6 18 GPIO_ACTIVE_HIGH>; reset-gpio = <&gpio3 13 GPIO_ACTIVE_LOW>; }; @@ -800,12 +811,12 @@ pinctrl-0 = <&pinctrl_usdhc3>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; + vmmc-supply = <®_sdio>; no-1-8-v; }; /* SDMMC */ &usdhc4 { - /* Internal eMMC, optional on some boards */ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc4>; bus-width = <8>; @@ -814,6 +825,7 @@ non-removable; vmmc-supply = <®_3p3v_s0>; vqmmc-supply = <®_1p8v_s0>; + status = "okay"; }; &wdog1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi index 238f3af42822..807f3c95e3ce 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6a.dtsi @@ -22,12 +22,16 @@ compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - #address-cells = <1>; - #size-cells = <1>; vcc-supply = <®_mba6_3p3v>; - mba_mac_address: mac-address@20 { - reg = <0x20 0x6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi index a587bc88f76f..789733a45b95 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-mba6b.dtsi @@ -32,12 +32,16 @@ compatible = "atmel,24c64"; reg = <0x57>; pagesize = <32>; - #address-cells = <1>; - #size-cells = <1>; vcc-supply = <®_mba6_3p3v>; - mba_mac_address: mac-address@20 { - reg = <0x20 0x6>; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + mba_mac_address: mac-address@20 { + reg = <0x20 0x6>; + }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index 6656e2e762a1..0a3deaf92eea 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -786,7 +786,7 @@ display-timings { native-mode = <&timing0>; - timing0: hsd100pxn1 { + timing0: timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi index 79f2354886b7..ded241a39906 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lcd.dtsi @@ -110,7 +110,7 @@ }; display-timings { - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -126,8 +126,7 @@ pixelclk-active = <0>; }; - ETV570 { - u-boot,panel-name = "edt,et057090dhu"; + timing-etv570 { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -143,8 +142,7 @@ pixelclk-active = <0>; }; - ET0350 { - u-boot,panel-name = "edt,et0350g0dh6"; + timing-et0350 { clock-frequency = <6413760>; hactive = <320>; vactive = <240>; @@ -160,8 +158,7 @@ pixelclk-active = <0>; }; - ET0430 { - u-boot,panel-name = "edt,et0430g0dh6"; + timing-et0430 { clock-frequency = <9009000>; hactive = <480>; vactive = <272>; @@ -177,7 +174,7 @@ pixelclk-active = <1>; }; - ET0500 { + timing-et0500 { clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -193,8 +190,7 @@ pixelclk-active = <0>; }; - ET0700 { /* same as ET0500 */ - u-boot,panel-name = "edt,etm0700g0dh6"; + timing-et0700 { /* same as ET0500 */ clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -210,7 +206,7 @@ pixelclk-active = <0>; }; - ETQ570 { + timing-etq570 { clock-frequency = <6596040>; hactive = <320>; vactive = <240>; @@ -226,8 +222,7 @@ pixelclk-active = <0>; }; - CoMTFT { /* same as ET0700 but with inverted pixel clock */ - u-boot,panel-name = "edt,etm0700g0edh6"; + timing-comtft { /* same as ET0700 but with inverted pixel clock */ clock-frequency = <33264000>; hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi index 2ca2eb37e14f..4eb53d5677a6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6-lvds.dtsi @@ -127,8 +127,7 @@ }; display-timings { - hsd100pxn1 { - u-boot,panel-name = "hannstar,hsd100pxn1"; + timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; @@ -142,7 +141,7 @@ pixelclk-active = <1>; }; - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -158,8 +157,7 @@ pixelclk-active = <0>; }; - nl12880bc20 { - u-boot,panel-name = "nlt,nl12880bc20-spwg-24"; + timing-nl12880bc20 { clock-frequency = <71000000>; hactive = <1280>; vactive = <800>; @@ -175,8 +173,7 @@ pixelclk-active = <1>; }; - ET0700 { - u-boot,panel-name = "edt,etm0700g0dh6"; + timing-et0700 { clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -192,8 +189,7 @@ pixelclk-active = <0>; }; - ETV570 { - u-boot,panel-name = "edt,et057090dhu"; + timing-etv570 { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -224,7 +220,7 @@ }; display-timings { - hsd100pxn1 { + timing-hsd100pxn1 { clock-frequency = <65000000>; hactive = <1024>; vactive = <768>; @@ -238,7 +234,7 @@ pixelclk-active = <1>; }; - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -254,7 +250,7 @@ pixelclk-active = <0>; }; - nl12880bc20 { + timing-nl12880bc20 { clock-frequency = <71000000>; hactive = <1280>; vactive = <800>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index 1db146ac1c17..864173e30709 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -405,7 +405,7 @@ status = "okay"; display-timings { - VGA { + timing-vga { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -421,7 +421,7 @@ pixelclk-active = <1>; }; - ETV570 { + timing-etv570 { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; @@ -437,7 +437,7 @@ pixelclk-active = <1>; }; - ET0350 { + timing-et0350 { clock-frequency = <6413760>; hactive = <320>; vactive = <240>; @@ -453,7 +453,7 @@ pixelclk-active = <1>; }; - ET0430 { + timing-et0430 { clock-frequency = <9009000>; hactive = <480>; vactive = <272>; @@ -469,7 +469,7 @@ pixelclk-active = <0>; }; - ET0500 { + timing-et0500 { clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -485,7 +485,7 @@ pixelclk-active = <1>; }; - ET0700 { /* same as ET0500 */ + timing-et0700 { /* same as ET0500 */ clock-frequency = <33264000>; hactive = <800>; vactive = <480>; @@ -501,7 +501,7 @@ pixelclk-active = <1>; }; - ETQ570 { + timing-etq570 { clock-frequency = <6596040>; hactive = <320>; vactive = <240>; diff --git a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts index 5485fe118dc4..d38183edf0fd 100644 --- a/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts +++ b/arch/arm/boot/dts/nxp/mxs/imx28-tx28.dts @@ -323,7 +323,6 @@ display-timings { native-mode = <&timing5>; timing0: timing0 { - panel-name = "VGA"; clock-frequency = <25175000>; hactive = <640>; vactive = <480>; @@ -340,7 +339,6 @@ }; timing1: timing1 { - panel-name = "ETV570"; clock-frequency = <25175000>; hactive = <640>; vactive = <480>; @@ -357,7 +355,6 @@ }; timing2: timing2 { - panel-name = "ET0350"; clock-frequency = <6500000>; hactive = <320>; vactive = <240>; @@ -374,7 +371,6 @@ }; timing3: timing3 { - panel-name = "ET0430"; clock-frequency = <9000000>; hactive = <480>; vactive = <272>; @@ -391,7 +387,6 @@ }; timing4: timing4 { - panel-name = "ET0500", "ET0700"; clock-frequency = <33260000>; hactive = <800>; vactive = <480>; @@ -408,7 +403,6 @@ }; timing5: timing5 { - panel-name = "ETQ570"; clock-frequency = <6400000>; hactive = <320>; vactive = <240>; diff --git a/arch/arm/boot/dts/qcom/Makefile b/arch/arm/boot/dts/qcom/Makefile index e2e922bdc9e9..f06c6d425e91 100644 --- a/arch/arm/boot/dts/qcom/Makefile +++ b/arch/arm/boot/dts/qcom/Makefile @@ -6,6 +6,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-apq8026-huawei-sturgeon.dtb \ qcom-apq8026-lg-lenok.dtb \ qcom-apq8026-samsung-matisse-wifi.dtb \ + qcom-apq8026-samsung-milletwifi.dtb \ qcom-apq8060-dragonboard.dtb \ qcom-apq8064-cm-qs600.dtb \ qcom-apq8064-ifc6410.dtb \ @@ -27,6 +28,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8226-microsoft-dempsey.dtb \ qcom-msm8226-microsoft-makepeace.dtb \ qcom-msm8226-microsoft-moneypenny.dtb \ + qcom-msm8226-samsung-ms013g.dtb \ qcom-msm8226-samsung-s3ve3g.dtb \ qcom-msm8660-surf.dtb \ qcom-msm8916-samsung-e5.dtb \ @@ -41,12 +43,15 @@ dtb-$(CONFIG_ARCH_QCOM) += \ qcom-msm8960-cdp.dtb \ qcom-msm8960-samsung-expressatt.dtb \ qcom-msm8974-lge-nexus5-hammerhead.dtb \ + qcom-msm8974-samsung-hlte.dtb \ qcom-msm8974-sony-xperia-rhine-amami.dtb \ qcom-msm8974-sony-xperia-rhine-honami.dtb \ qcom-msm8974pro-fairphone-fp2.dtb \ + qcom-msm8974pro-htc-m8.dtb \ qcom-msm8974pro-oneplus-bacon.dtb \ qcom-msm8974pro-samsung-klte.dtb \ qcom-msm8974pro-samsung-kltechn.dtb \ + qcom-msm8974pro-sony-xperia-shinano-aries.dtb \ qcom-msm8974pro-sony-xperia-shinano-castor.dtb \ qcom-msm8974pro-sony-xperia-shinano-leo.dtb \ qcom-mdm9615-wp8548-mangoh-green.dtb \ diff --git a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts index 029e1b1659c9..5dbca83f2230 100644 --- a/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts +++ b/arch/arm/boot/dts/qcom/msm8226-motorola-falcon.dts @@ -96,6 +96,35 @@ }; }; +&blsp1_i2c2 { + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak8963"; + reg = <0xc>; + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + vdd-supply = <&pm8226_l19>; + vid-supply = <&pm8226_lvs1>; + pinctrl-0 = <&mag_int_default &mag_reset_default>; + pinctrl-names = "default"; + }; + + accelerometer@19 { + compatible = "st,lis3dh-accel"; + reg = <0x19>; + interrupts-extended = <&tlmm 63 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8226_l19>; + vddio-supply = <&pm8226_lvs1>; + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "-1"; + st,drdy-int-pin = <1>; + }; +}; + &blsp1_i2c3 { status = "okay"; @@ -321,6 +350,30 @@ }; &tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio63"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; + + mag_int_default: mag-int-default-state { + pins = "gpio66"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; + + mag_reset_default: mag-reset-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + reg_lcd_default: reg-lcd-default-state { pins = "gpio31", "gpio33"; function = "gpio"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts new file mode 100644 index 000000000000..7d519156d91d --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-apq8026-samsung-milletwifi.dts @@ -0,0 +1,573 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Matti Lehtimäki <matti.lehtimaki@gmail.com> + * Copyright (c) 2023, Bryant Mairs <bryant@mai.rs> + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/power/summit,smb347-charger.h> +#include "qcom-msm8226.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &adsp_region; +/delete-node/ &smem_region; + +/ { + model = "Samsung Galaxy Tab 4 8.0 Wi-Fi"; + compatible = "samsung,milletwifi", "qcom,apq8026"; + chassis-type = "tablet"; + + aliases { + display0 = &framebuffer0; + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + }; + + chosen { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + stdout-path = "display0"; + + framebuffer0: framebuffer@3200000 { + compatible = "simple-framebuffer"; + reg = <0x03200000 0x800000>; + width = <800>; + height = <1280>; + stride = <(800 * 3)>; + format = "r8g8b8"; + }; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + event-hall-sensor { + label = "Cover"; + gpios = <&tlmm 37 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + key-home { + label = "Home"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + debounce-interval = <15>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + i2c-backlight { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&backlight_i2c_default_state>; + pinctrl-names = "default"; + + i2c-gpio,delay-us = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + enable-supply = <®_backlight_vddio>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x3f>; + + /* + * Change transition duration: 200ms, Change + * transition strength: heavy, PWM hysteresis: + * 1-bit w/ 8-bit resolution + */ + rom-a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + + /* + * PWM phase configuration: 3-phase/3 drivers + * (0, 120deg, 240deg, -, -, -), + * PWM frequency: 9616Hz (10-bit) + */ + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x34>; + }; + + /* + * Enable LED drivers 2 & 3, Boot inductor + * current limit: 1.5A/2.6A + */ + rom-a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xfa>; + }; + }; + }; + + reg_backlight_vddio: regulator-backlight-vddio { + compatible = "regulator-fixed"; + regulator-name = "backlight_vddio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&backlight_vddio_default_state>; + pinctrl-names = "default"; + }; + + reg_tsp_1p8v: regulator-tsp-1p8v { + compatible = "regulator-fixed"; + regulator-name = "tsp_1p8v"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + gpio = <&tlmm 114 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en1_default_state>; + pinctrl-names = "default"; + }; + + reg_tsp_3p3v: regulator-tsp-3p3v { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default_state>; + pinctrl-names = "default"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + framebuffer@3200000 { + reg = <0x03200000 0x800000>; + no-map; + }; + + mpss_region: mpss@8400000 { + reg = <0x08400000 0x1f00000>; + no-map; + }; + + mba_region: mba@a300000 { + reg = <0x0a300000 0x100000>; + no-map; + }; + + reserved@cb00000 { + reg = <0x0cb00000 0x700000>; + no-map; + }; + + wcnss_region: wcnss@d200000 { + reg = <0x0d200000 0x700000>; + no-map; + }; + + adsp_region: adsp@d900000 { + reg = <0x0d900000 0x1800000>; + no-map; + }; + + venus@f100000 { + reg = <0x0f100000 0x500000>; + no-map; + }; + + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + + reserved@fb00000 { + reg = <0x0fb00000 0x260000>; + no-map; + }; + + rfsa@fd60000 { + reg = <0x0fd60000 0x20000>; + no-map; + }; + + rmtfs@fd80000 { + compatible = "qcom,rmtfs-mem"; + reg = <0x0fd80000 0x180000>; + no-map; + + qcom,client-id = <1>; + }; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + accelerometer@1d { + compatible = "st,lis2hh12"; + reg = <0x1d>; + + interrupts-extended = <&tlmm 54 IRQ_TYPE_LEVEL_HIGH>; + + pinctrl-0 = <&accel_int_default_state>; + pinctrl-names = "default"; + + vdd-supply = <&pm8226_l19>; + vddio-supply = <&pm8226_lvs1>; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "1"; + + st,drdy-int-pin = <1>; + }; +}; + +&blsp1_i2c3 { + status = "okay"; + + charger@6a { + compatible = "summit,smb358"; + reg = <0x6a>; + + interrupts-extended = <&tlmm 115 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&charger_int_default_state>; + pinctrl-names = "default"; + + summit,enable-usb-charging; + summit,enable-charge-control = <SMB3XX_CHG_ENABLE_SW>; + summit,fast-voltage-threshold-microvolt = <3000000>; + summit,chip-temperature-threshold-celsius = <130>; + summit,usb-current-limit-microamp = <1500000>; + }; +}; + +&blsp1_i2c4 { + status = "okay"; + + muic: usb-switch@25 { + compatible = "siliconmitus,sm5502-muic"; + reg = <0x25>; + + interrupts-extended = <&tlmm 67 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&muic_int_default_state>; + pinctrl-names = "default"; + }; +}; + +&blsp1_i2c5 { + status = "okay"; + + touchscreen@48 { + compatible = "melfas,mms252", "melfas,mms114"; + reg = <0x48>; + interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + avdd-supply = <®_tsp_3p3v>; + vdd-supply = <®_tsp_1p8v>; + linux,keycodes = <KEY_APPSELECT KEY_BACK>; + + pinctrl-0 = <&tsp_int_rst_default_state>; + pinctrl-names = "default"; + }; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + regulator-always-on; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8226_l18>; + vqmmc-supply = <&pm8226_l21>; + + bus-width = <4>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sdhc2_default_state>, <&sdc2_cd_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&tlmm { + accel_int_default_state: accel-int-default-state { + pins = "gpio54"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_i2c_default_state: backlight-i2c-default-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_vddio_default_state: backlight-vddio-default-state { + pins = "gpio74"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + charger_int_default_state: charger-int-default-state { + pins = "gpio115"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + muic_int_default_state: muic-int-default-state { + pins = "gpio67"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdc2_cd_default_state: sdc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en_default_state: tsp-en-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en1_default_state: tsp-en1-default-state { + pins = "gpio114"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_rst_default_state: tsp-int-rst-default-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <10>; + bias-pull-up; + }; +}; + +&usb { + extcon = <&muic>, <&muic>; + status = "okay"; +}; + +&usb_hs_phy { + extcon = <&muic>; + v1p8-supply = <&pm8226_l10>; + v3p3-supply = <&pm8226_l20>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 11e60b74c3c9..769e151747c3 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -666,12 +666,12 @@ qcom,controller-type = "pmic-arbiter"; }; - qfprom: qfprom@700000 { + qfprom: efuse@700000 { compatible = "qcom,apq8064-qfprom", "qcom,qfprom"; reg = <0x00700000 0x1000>; #address-cells = <1>; #size-cells = <1>; - ranges; + tsens_calib: calib@404 { reg = <0x404 0x10>; }; @@ -684,7 +684,6 @@ compatible = "qcom,gcc-apq8064", "syscon"; reg = <0x00900000 0x4000>; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; clocks = <&cxo_board>, <&pxo_board>, @@ -993,7 +992,7 @@ reg = <0x1a400000 0x100>; }; - gpu: adreno-3xx@4300000 { + gpu: gpu@4300000 { compatible = "qcom,adreno-320.2", "qcom,adreno"; reg = <0x04300000 0x20000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index ca53dff820ef..2b52e5d5eb51 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -245,7 +245,7 @@ reg = <0xfc190000 0x10000>; }; - qfprom: qfprom@fc4bc000 { + qfprom: efuse@fc4bc000 { compatible = "qcom,apq8084-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 0fb65f2bbcdf..56415ab34083 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -187,7 +187,6 @@ gcc: clock-controller@1800000 { compatible = "qcom,gcc-ipq4019"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x1800000 0x60000>; clocks = <&xo>, <&sleep_clk>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index f128510d8445..da0fd75f4711 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -372,7 +372,7 @@ qcom,controller-type = "pmic-arbiter"; }; - qfprom: qfprom@700000 { + qfprom: efuse@700000 { compatible = "qcom,ipq8064-qfprom", "qcom,qfprom"; reg = <0x00700000 0x1000>; #address-cells = <1>; @@ -519,7 +519,6 @@ reg = <0x00900000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; - #power-domain-cells = <1>; tsens: thermal-sensor { compatible = "qcom,ipq8064-tsens"; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index 34c60994d026..573feb3218c3 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -102,7 +102,6 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-mdm9615"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&cxo_board>, diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts new file mode 100644 index 000000000000..2ecc5983d365 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8226-samsung-ms013g.dts @@ -0,0 +1,386 @@ +// SPDX-License-Identifier: BSD-3-Clause + +/dts-v1/; + +#include "qcom-msm8226.dtsi" +#include "pm8226.dtsi" + +/delete-node/ &smem_region; + +/ { + model = "Samsung Galaxy Grand 2"; + compatible = "samsung,ms013g", "qcom,msm8226"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ + serial0 = &blsp1_uart3; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-hall-sensor { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + + label = "GPIO Hall Effect Sensor"; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 50 GPIO_ACTIVE_LOW>; + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + linux,can-disable; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + label = "GPIO Buttons"; + + button-volume-up { + label = "Volume Up"; + gpios = <&tlmm 106 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + }; + + button-volume-down { + label = "Volume Down"; + gpios = <&tlmm 107 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + }; + + button-home { + label = "Home Key"; + gpios = <&tlmm 108 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + }; + }; + + reg_motor_vdd: regulator-motor-vdd { + compatible = "regulator-fixed"; + regulator-name = "motor_vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 111 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&motor_en_default>; + pinctrl-names = "default"; + }; + + reg_vdd_tsp_a: regulator-vdd-tsp-a { + compatible = "regulator-fixed"; + regulator-name = "tsp_3p3v"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&tsp_en_default>; + pinctrl-names = "default"; + }; + + reserved-memory { + smem_region: smem@fa00000 { + reg = <0x0fa00000 0x100000>; + no-map; + }; + }; + + vibrator { + compatible = "regulator-haptic"; + haptic-supply = <®_motor_vdd>; + min-microvolt = <3300000>; + max-microvolt = <3300000>; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + accelerometer@18 { + compatible = "bosch,bma255"; + reg = <0x18>; + interrupts-extended = <&tlmm 64 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&pm8226_l19>; + vddio-supply = <&pm8226_lvs1>; + + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + + mount-matrix = "0", "1", "0", + "-1", "0", "0", + "0", "0", "-1"; + }; +}; + +&blsp1_i2c5 { + status = "okay"; + + touchscreen@20 { + compatible = "zinitix,bt541"; + + reg = <0x20>; + interrupts-extended = <&tlmm 17 IRQ_TYPE_EDGE_FALLING>; + + touchscreen-size-x = <720>; + touchscreen-size-y = <1280>; + + vcca-supply = <®_vdd_tsp_a>; + vdd-supply = <&pm8226_lvs1>; + + pinctrl-0 = <&tsp_int_default>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart3 { + status = "okay"; +}; + +&rpm_requests { + regulators { + compatible = "qcom,rpm-pm8226-regulators"; + + pm8226_s3: s3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_s4: s4 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2200000>; + }; + + pm8226_s5: s5 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1150000>; + }; + + pm8226_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8226_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l3: l3 { + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1337500>; + }; + + pm8226_l4: l4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l5: l5 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8226_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l7: l7 { + regulator-min-microvolt = <1850000>; + regulator-max-microvolt = <1850000>; + }; + + pm8226_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l9: l9 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8226_l14: l14 { + regulator-min-microvolt = <2750000>; + regulator-max-microvolt = <2750000>; + }; + + pm8226_l15: l15 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + pm8226_l16: l16 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3350000>; + }; + + pm8226_l17: l17 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-always-on; + }; + + pm8226_l18: l18 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l19: l19 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8226_l20: l20 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + + pm8226_l21: l21 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-allow-set-load; + }; + + pm8226_l22: l22 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_l23: l23 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8226_l24: l24 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1350000>; + }; + + pm8226_l25: l25 { + regulator-min-microvolt = <1775000>; + regulator-max-microvolt = <2125000>; + }; + + pm8226_l26: l26 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1300000>; + }; + + pm8226_l27: l27 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8226_l28: l28 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8226_lvs1: lvs1 {}; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8226_l17>; + vqmmc-supply = <&pm8226_l6>; + + bus-width = <8>; + non-removable; + + status = "okay"; +}; + +&sdhc_2 { + vmmc-supply = <&pm8226_l18>; + vqmmc-supply = <&pm8226_l21>; + + bus-width = <4>; + cd-gpios = <&tlmm 38 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&sdhc2_default_state &sdhc2_cd_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio64"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio50"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + gpio_keys_default: gpio-keys-default-state { + pins = "gpio106", "gpio107", "gpio108"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + + motor_en_default: motor-en-default-state { + pins = "gpio111"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + sdhc2_cd_default: sdhc2-cd-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_en_default: tsp-en-default-state { + pins = "gpio31"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + tsp_int_default: tsp-int-default-state { + pins = "gpio17"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 270973e85625..b2f92ad6499a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -635,7 +635,7 @@ reg = <0xfc4ab000 0x4>; }; - qfprom: qfprom@fc4bc000 { + qfprom: efuse@fc4bc000 { compatible = "qcom,msm8226-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x1000>; #address-cells = <1>; @@ -1046,7 +1046,7 @@ }; }; - gpu: adreno@fdb00000 { + gpu: gpu@fdb00000 { compatible = "qcom,adreno-305.18", "qcom,adreno"; reg = <0xfdb00000 0x10000>; reg-names = "kgsl_3d0_reg_memory"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi index 455ba4bf1bf4..a66c474cd1aa 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -113,7 +113,6 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8660"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&pxo_board>, <&cxo_board>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts index 0cbe2d2fbbb1..376a33125941 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8926-motorola-peregrine.dts @@ -29,6 +29,10 @@ height = <1280>; stride = <(720 * 3)>; format = "r8g8b8"; + vsp-supply = <®_lcd_pos>; + vsn-supply = <®_lcd_neg>; + vdd-supply = <&pm8226_l28>; + vddio-supply = <&vddio_disp_vreg>; }; }; @@ -51,6 +55,18 @@ }; }; + vddio_disp_vreg: regulator-vddio-disp { + compatible = "regulator-fixed"; + regulator-name = "vddio_disp"; + gpio = <&tlmm 34 GPIO_ACTIVE_HIGH>; + startup-delay-us = <300>; + enable-active-high; + regulator-boot-on; + vin-supply = <&pm8226_l8>; + pinctrl-0 = <&disp_vddio_default>; + pinctrl-names = "default"; + }; + reserved-memory { #address-cells = <1>; #size-cells = <1>; @@ -68,12 +84,67 @@ }; }; +&blsp1_i2c2 { + clock-frequency = <100000>; + status = "okay"; + + magnetometer@c { + compatible = "asahi-kasei,ak8963"; + reg = <0xc>; + interrupts-extended = <&tlmm 38 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; + vdd-supply = <&pm8226_l19>; + pinctrl-0 = <&mag_int_default &mag_reset_default>; + pinctrl-names = "default"; + }; + + accelerometer@18 { + compatible = "st,lis3dh-accel"; + reg = <0x18>; + interrupts-extended = <&tlmm 1 IRQ_TYPE_EDGE_FALLING>; + vdd-supply = <&pm8226_l19>; + pinctrl-0 = <&accel_int_default>; + pinctrl-names = "default"; + st,drdy-int-pin = <1>; + }; +}; + &blsp1_i2c3 { + clock-frequency = <400000>; status = "okay"; + regulator@3e { + compatible = "ti,tps65132"; + reg = <0x3e>; + pinctrl-0 = <®_lcd_default>; + pinctrl-names = "default"; + + reg_lcd_pos: outp { + regulator-name = "outp"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 31 GPIO_ACTIVE_HIGH>; + }; + + reg_lcd_neg: outn { + regulator-name = "outn"; + regulator-min-microvolt = <4000000>; + regulator-max-microvolt = <6000000>; + regulator-active-discharge = <1>; + regulator-boot-on; + enable-gpios = <&tlmm 33 GPIO_ACTIVE_HIGH>; + }; + }; + sensor@48 { compatible = "ti,tmp108"; reg = <0x48>; + interrupts-extended = <&tlmm 13 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&temp_alert_default>; + pinctrl-names = "default"; + #thermal-sensor-cells = <0>; }; }; @@ -278,6 +349,56 @@ status = "okay"; }; +&tlmm { + accel_int_default: accel-int-default-state { + pins = "gpio1"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; + + disp_vddio_default: disp-vddio-default-state { + pins = "gpio34"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + mag_int_default: mag-int-default-state { + pins = "gpio38"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; + + mag_reset_default: mag-reset-default-state { + pins = "gpio62"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + reg_lcd_default: reg-lcd-default-state { + pins = "gpio31", "gpio33"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + temp_alert_default: temp-alert-default-state { + pins = "gpio13"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + output-disable; + }; +}; + &usb { extcon = <&smbb>; dr_mode = "peripheral"; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index 922f9e49468a..ebc43c5c6e5f 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -47,9 +47,9 @@ }; }; - memory { + memory@80000000 { device_type = "memory"; - reg = <0x0 0x0>; + reg = <0x80000000 0>; }; cpu-pmu { @@ -129,7 +129,6 @@ gcc: clock-controller@900000 { compatible = "qcom,gcc-msm8960"; #clock-cells = <1>; - #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; clocks = <&cxo_board>, diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index 4aaae8537a3f..fdb6e22986cf 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -182,7 +182,7 @@ status = "okay"; clock-frequency = <355000>; - led-controller@38 { + backlight: led-controller@38 { compatible = "ti,lm3630a"; status = "okay"; reg = <0x38>; @@ -272,6 +272,8 @@ reg = <0>; compatible = "lg,acx467akm-7"; + backlight = <&backlight>; + pinctrl-names = "default"; pinctrl-0 = <&panel_pin>; @@ -328,7 +330,7 @@ power-source = <PM8941_GPIO_S3>; }; - otg { + otg-hog { gpio-hog; gpios = <35 GPIO_ACTIVE_HIGH>; output-high; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts new file mode 100644 index 000000000000..903bb4d12513 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-samsung-hlte.dts @@ -0,0 +1,401 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/qcom,pmic-gpio.h> + +/ { + model = "Samsung Galaxy Note 3"; + compatible = "samsung,hlte", "qcom,msm8974"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; /* SDC1 eMMC slot */ + mmc1 = &sdhc_3; /* SDC3 SD card slot */ + serial0 = &blsp1_uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_pin_a>; + pinctrl-names = "default"; + + key-home { + label = "Home Key"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_HOMEPAGE>; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <15>; + }; + }; + + touch_ldo: regulator-touch { + compatible = "regulator-fixed"; + regulator-name = "touch-ldo"; + + gpio = <&pm8941_gpios 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + + pinctrl-0 = <&touch_ldo_pin>; + pinctrl-names = "default"; + }; +}; + +&blsp1_i2c2 { + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + + interrupt-parent = <&pm8941_gpios>; + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&pm8941_l10>; + vio-supply = <&touch_ldo>; + + pinctrl-0 = <&touch_pin>; + pinctrl-names = "default"; + + syna,startup-delay-ms = <100>; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +&blsp2_i2c6 { + status = "okay"; + + fuelgauge@36 { + compatible = "maxim,max17048"; + reg = <0x36>; + + maxim,double-soc; + maxim,rcomp = /bits/ 8 <0x56>; + + interrupt-parent = <&pm8941_gpios>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&fuelgauge_pin>; + pinctrl-names = "default"; + }; +}; + +&blsp1_uart2 { + status = "okay"; +}; + +&pm8941_gpios { + gpio_keys_pin_a: gpio-keys-active-state { + pins = "gpio2", "gpio3", "gpio5"; + function = "normal"; + bias-pull-up; + power-source = <PM8941_GPIO_S3>; + }; + + fuelgauge_pin: fuelgauge-int-state { + pins = "gpio26"; + function = "normal"; + bias-disable; + input-enable; + power-source = <PM8941_GPIO_S3>; + }; + + touch_pin: touchscreen-int-state { + pins = "gpio30"; + function = "normal"; + bias-disable; + input-enable; + power-source = <PM8941_GPIO_S3>; + }; + + touch_ldo_pin: touchscreen-ldo-state { + pins = "gpio9"; + function = "normal"; + output-high; + power-source = <PM8941_GPIO_S3>; + qcom,drive-strength = <PMIC_GPIO_STRENGTH_HIGH>; + }; +}; + +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; + status = "okay"; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; + status = "okay"; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-0 = <&sdhc1_pin_a>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&sdhc_3 { + max-frequency = <100000000>; + + vmmc-supply = <&pm8941_l21>; + vqmmc-supply = <&pm8941_l21>; + + pinctrl-0 = <&sdhc3_pin_a>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&tlmm { + sdhc1_pin_a: sdhc1-pin-active-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <4>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <4>; + bias-pull-up; + }; + }; + + sdhc3_pin_a: sdhc3-pin-active-state { + pins = "gpio35", "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "sdc3"; + drive-strength = <8>; + bias-disable; + }; +}; + +&usb { + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + + hnp-disable; + srp-disable; + adp-disable; + + status = "okay"; +}; + +&usb_hs1_phy { + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + + qcom,init-seq = /bits/ 8 <0x1 0x64>; + + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 5651bb31bd54..15568579459a 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -132,7 +132,7 @@ smd-edge { interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 0>; + mboxes = <&apcs 0>; qcom,smd-edge = <15>; rpm_requests: rpm-requests { @@ -219,7 +219,7 @@ interrupt-parent = <&intc>; interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 10>; + mboxes = <&apcs 10>; qcom,local-pid = <0>; qcom,remote-pid = <2>; @@ -244,7 +244,7 @@ interrupt-parent = <&intc>; interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 14>; + mboxes = <&apcs 14>; qcom,local-pid = <0>; qcom,remote-pid = <1>; @@ -269,7 +269,7 @@ interrupt-parent = <&intc>; interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 18>; + mboxes = <&apcs 18>; qcom,local-pid = <0>; qcom,remote-pid = <4>; @@ -294,9 +294,7 @@ #address-cells = <1>; #size-cells = <0>; - qcom,ipc-1 = <&apcs 8 13>; - qcom,ipc-2 = <&apcs 8 9>; - qcom,ipc-3 = <&apcs 8 19>; + mboxes = <0>, <&apcs 13>, <&apcs 9>, <&apcs 19>; apps_smsm: apps@0 { reg = <0>; @@ -343,9 +341,11 @@ <0xf9002000 0x1000>; }; - apcs: syscon@f9011000 { - compatible = "syscon"; + apcs: mailbox@f9011000 { + compatible = "qcom,msm8974-apcs-kpss-global", + "qcom,msm8994-apcs-kpss-global", "syscon"; reg = <0xf9011000 0x1000>; + #mbox-cells = <1>; }; saw_l2: power-manager@f9012000 { @@ -757,7 +757,7 @@ smd-edge { interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 17>; + mboxes = <&apcs 17>; qcom,smd-edge = <6>; wcnss { @@ -1233,7 +1233,7 @@ reg = <0xfc4ab000 0x4>; }; - qfprom: qfprom@fc4bc000 { + qfprom: efuse@fc4bc000 { compatible = "qcom,msm8974-qfprom", "qcom,qfprom"; reg = <0xfc4bc000 0x2100>; #address-cells = <1>; @@ -1576,7 +1576,7 @@ smd-edge { interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 12>; + mboxes = <&apcs 12>; qcom,smd-edge = <0>; label = "modem"; @@ -2129,7 +2129,7 @@ }; }; - gpu: adreno@fdb00000 { + gpu: gpu@fdb00000 { compatible = "qcom,adreno-330.1", "qcom,adreno"; reg = <0xfdb00000 0x10000>; reg-names = "kgsl_3d0_reg_memory"; @@ -2213,7 +2213,7 @@ smd-edge { interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; - qcom,ipc = <&apcs 8 8>; + mboxes = <&apcs 8>; qcom,smd-edge = <1>; label = "lpass"; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts new file mode 100644 index 000000000000..b896cc1ad6f7 --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-htc-m8.dts @@ -0,0 +1,353 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include "qcom-msm8974pro.dtsi" +#include "pm8841.dtsi" +#include "pm8941.dtsi" +#include <dt-bindings/input/input.h> + +/ { + model = "HTC One (M8)"; + compatible = "htc,m8", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "handset"; + + aliases { + mmc0 = &sdhc_1; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>; + pinctrl-names = "default"; + + key-volume-down { + label = "volume_down"; + gpios = <&tlmm 27 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEDOWN>; + debounce-interval = <20>; + wakeup-source; + }; + + key-volume-up { + label = "volume_up"; + gpios = <&tlmm 28 GPIO_ACTIVE_LOW>; + linux,code = <KEY_VOLUMEUP>; + debounce-interval = <20>; + wakeup-source; + }; + }; + + vreg_boost: vreg-boost { + compatible = "regulator-fixed"; + + regulator-name = "vreg-boost"; + regulator-min-microvolt = <3150000>; + regulator-max-microvolt = <3150000>; + + regulator-always-on; + regulator-boot-on; + + gpio = <&pm8941_gpios 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&boost_bypass_n_pin>; + pinctrl-names = "default"; + }; + + vreg_vph_pwr: vreg-vph-pwr { + compatible = "regulator-fixed"; + regulator-name = "vph-pwr"; + + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + + regulator-always-on; + }; +}; + +&pm8941_vib { + status = "okay"; +}; + +&pronto { + vddmx-supply = <&pm8841_s1>; + vddcx-supply = <&pm8841_s2>; + vddpx-supply = <&pm8941_s3>; + + pinctrl-0 = <&wcnss_pin_a>; + pinctrl-names = "default"; + + status = "okay"; + + iris { + vddxo-supply = <&pm8941_l6>; + vddrfa-supply = <&pm8941_l11>; + vddpa-supply = <&pm8941_l19>; + vdddig-supply = <&pm8941_s3>; + }; + + smd-edge { + qcom,remote-pid = <4>; + label = "pronto"; + + wcnss { + status = "okay"; + }; + }; +}; + +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <815000>; + regulator-max-microvolt = <900000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pm8941-regulators"; + + vdd_l1_l3-supply = <&pm8941_s1>; + vdd_l2_lvs1_2_3-supply = <&pm8941_s3>; + vdd_l4_l11-supply = <&pm8941_s1>; + vdd_l5_l7-supply = <&pm8941_s2>; + vdd_l6_l12_l14_l15-supply = <&pm8941_s2>; + vdd_l8_l16_l18_l19-supply = <&vreg_vph_pwr>; + vdd_l9_l10_l17_l22-supply = <&vreg_boost>; + vdd_l13_l20_l23_l24-supply = <&vreg_boost>; + vdd_l21-supply = <&vreg_boost>; + + pm8941_s1: s1 { + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_s2: s2 { + regulator-min-microvolt = <2150000>; + regulator-max-microvolt = <2150000>; + regulator-boot-on; + }; + + pm8941_s3: s3 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l1: l1 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l2: l2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l3: l3 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + pm8941_l4: l4 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1225000>; + }; + + pm8941_l5: l5 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l6: l6 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l7: l7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + }; + + pm8941_l8: l8 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l9: l9 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l10: l10 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + }; + + pm8941_l11: l11 { + regulator-min-microvolt = <1225000>; + regulator-max-microvolt = <1350000>; + }; + + pm8941_l12: l12 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + pm8941_l13: l13 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l14: l14 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + pm8941_l15: l15 { + regulator-min-microvolt = <2050000>; + regulator-max-microvolt = <2050000>; + }; + + pm8941_l16: l16 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <2700000>; + }; + + pm8941_l17: l17 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l18: l18 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <2850000>; + }; + + pm8941_l19: l19 { + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <3350000>; + }; + + pm8941_l20: l20 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-system-load = <200000>; + regulator-allow-set-load; + regulator-boot-on; + }; + + pm8941_l21: l21 { + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + regulator-boot-on; + }; + + pm8941_l22: l22 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + pm8941_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + }; + + pm8941_l24: l24 { + regulator-min-microvolt = <3075000>; + regulator-max-microvolt = <3075000>; + regulator-boot-on; + }; + }; +}; + +&sdhc_1 { + vmmc-supply = <&pm8941_l20>; + vqmmc-supply = <&pm8941_s3>; + + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + +&smbb { + status = "okay"; +}; + +&tlmm { + gpio_keys_default: gpio-keys-default-state { + pins = "gpio27", "gpio28"; + function = "gpio"; + bias-pull-up; + }; + + sdc1_on: sdc1-on-state { + clk-pins { + pins = "sdc1_clk"; + drive-strength = <10>; + bias-disable; + }; + + cmd-data-pins { + pins = "sdc1_cmd", "sdc1_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; + + wcnss_pin_a: wcnss-pin-active-state { + pins = "gpio36", "gpio37", "gpio38", "gpio39", "gpio40"; + function = "wlan"; + drive-strength = <6>; + bias-pull-down; + }; +}; + +&usb { + phys = <&usb_hs1_phy>; + phy-select = <&tcsr 0xb000 0>; + extcon = <&smbb>, <&usb_id>; + vbus-supply = <&chg_otg>; + + hnp-disable; + srp-disable; + adp-disable; + + status = "okay"; +}; + +&usb_hs1_phy { + v1p8-supply = <&pm8941_l6>; + v3p3-supply = <&pm8941_l24>; + extcon = <&smbb>; + qcom,init-seq = /bits/ 8 <0x1 0x63>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts new file mode 100644 index 000000000000..2621c5928b6a --- /dev/null +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-aries.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +#include "qcom-msm8974pro-sony-xperia-shinano-common.dtsi" + +/ { + model = "Sony Xperia Z3 Compact"; + compatible = "sony,xperia-aries", "qcom,msm8974pro", "qcom,msm8974"; + chassis-type = "handset"; + + gpio-keys { + key-camera-snapshot { + label = "camera_snapshot"; + gpios = <&pm8941_gpios 3 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA>; + debounce-interval = <15>; + }; + + key-camera-focus { + label = "camera_focus"; + gpios = <&pm8941_gpios 4 GPIO_ACTIVE_LOW>; + linux,code = <KEY_CAMERA_FOCUS>; + debounce-interval = <15>; + }; + }; +}; + +&gpio_keys_pin_a { + pins = "gpio2", "gpio3", "gpio4", "gpio5"; +}; + +&smbb { + usb-charge-current-limit = <1500000>; + qcom,fast-charge-safe-current = <2100000>; + qcom,fast-charge-current-limit = <1800000>; + qcom,fast-charge-safe-voltage = <4400000>; + qcom,fast-charge-high-threshold-voltage = <4350000>; + qcom,auto-recharge-threshold-voltage = <4280000>; + qcom,minimum-input-voltage = <4200000>; + + status = "okay"; +}; + +&synaptics_touchscreen { + vio-supply = <&pm8941_s3>; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi index e129bb1bd6ec..6af7c71c7158 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974pro-sony-xperia-shinano-common.dtsi @@ -380,6 +380,8 @@ pm8941_l21: l21 { regulator-min-microvolt = <2950000>; regulator-max-microvolt = <2950000>; + regulator-system-load = <500000>; + regulator-allow-set-load; regulator-boot-on; }; diff --git a/arch/arm/boot/dts/renesas/r8a73a4.dtsi b/arch/arm/boot/dts/renesas/r8a73a4.dtsi index 9a2ae282a46b..85261684b5d5 100644 --- a/arch/arm/boot/dts/renesas/r8a73a4.dtsi +++ b/arch/arm/boot/dts/renesas/r8a73a4.dtsi @@ -58,6 +58,7 @@ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; tmu0: timer@e61e0000 { diff --git a/arch/arm/boot/dts/renesas/r8a7742.dtsi b/arch/arm/boot/dts/renesas/r8a7742.dtsi index d55c344c1cd2..3a5d6b434d09 100644 --- a/arch/arm/boot/dts/renesas/r8a7742.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7742.dtsi @@ -1938,6 +1938,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7743.dtsi b/arch/arm/boot/dts/renesas/r8a7743.dtsi index d917c0a971f5..8833898d5557 100644 --- a/arch/arm/boot/dts/renesas/r8a7743.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7743.dtsi @@ -1846,6 +1846,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7744.dtsi b/arch/arm/boot/dts/renesas/r8a7744.dtsi index 754859c38a93..c66c1102fb72 100644 --- a/arch/arm/boot/dts/renesas/r8a7744.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7744.dtsi @@ -1832,6 +1832,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7745.dtsi b/arch/arm/boot/dts/renesas/r8a7745.dtsi index 168298300490..6ddde364782b 100644 --- a/arch/arm/boot/dts/renesas/r8a7745.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7745.dtsi @@ -1636,6 +1636,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a77470.dtsi b/arch/arm/boot/dts/renesas/r8a77470.dtsi index 2375438d83c9..a8a12275c98a 100644 --- a/arch/arm/boot/dts/renesas/r8a77470.dtsi +++ b/arch/arm/boot/dts/renesas/r8a77470.dtsi @@ -1061,6 +1061,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7790.dtsi b/arch/arm/boot/dts/renesas/r8a7790.dtsi index 583b74a9f071..20e4d4c6e748 100644 --- a/arch/arm/boot/dts/renesas/r8a7790.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7790.dtsi @@ -2012,6 +2012,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7791.dtsi b/arch/arm/boot/dts/renesas/r8a7791.dtsi index de08ceb62230..f9c9e1d8f669 100644 --- a/arch/arm/boot/dts/renesas/r8a7791.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7791.dtsi @@ -1938,6 +1938,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7792.dtsi b/arch/arm/boot/dts/renesas/r8a7792.dtsi index 7defeb8e4cd1..dd3bc32668b7 100644 --- a/arch/arm/boot/dts/renesas/r8a7792.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7792.dtsi @@ -990,5 +990,6 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; }; diff --git a/arch/arm/boot/dts/renesas/r8a7793.dtsi b/arch/arm/boot/dts/renesas/r8a7793.dtsi index d32a9d5d3faa..24e66ddf37e0 100644 --- a/arch/arm/boot/dts/renesas/r8a7793.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7793.dtsi @@ -1517,6 +1517,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r8a7794.dtsi b/arch/arm/boot/dts/renesas/r8a7794.dtsi index f37f094cecc8..8e6386a79aea 100644 --- a/arch/arm/boot/dts/renesas/r8a7794.dtsi +++ b/arch/arm/boot/dts/renesas/r8a7794.dtsi @@ -1484,6 +1484,7 @@ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; /* External USB clock - can be overridden by the board */ diff --git a/arch/arm/boot/dts/renesas/r9a06g032.dtsi b/arch/arm/boot/dts/renesas/r9a06g032.dtsi index 45f60eeeaaa1..7548291c8d7e 100644 --- a/arch/arm/boot/dts/renesas/r9a06g032.dtsi +++ b/arch/arm/boot/dts/renesas/r9a06g032.dtsi @@ -316,6 +316,24 @@ data-width = <8>; }; + gmac1: ethernet@44000000 { + compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; + reg = <0x44000000 0x2000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", "eth_wake_irq", "eth_lpi"; + clocks = <&sysctrl R9A06G032_HCLK_GMAC0>; + clock-names = "stmmaceth"; + power-domains = <&sysctrl>; + snps,multicast-filter-bins = <256>; + snps,perfect-filter-entries = <128>; + tx-fifo-depth = <2048>; + rx-fifo-depth = <4096>; + pcs-handle = <&mii_conv1>; + status = "disabled"; + }; + gmac2: ethernet@44002000 { compatible = "renesas,r9a06g032-gmac", "renesas,rzn1-gmac", "snps,dwmac"; reg = <0x44002000 0x2000>; @@ -466,6 +484,7 @@ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; + interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; }; usbphy: usb-phy { diff --git a/arch/arm/boot/dts/rockchip/rk3036.dtsi b/arch/arm/boot/dts/rockchip/rk3036.dtsi index 04af224005f8..96279d1e02fe 100644 --- a/arch/arm/boot/dts/rockchip/rk3036.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3036.dtsi @@ -402,6 +402,7 @@ rockchip,grf = <&grf>; pinctrl-names = "default"; pinctrl-0 = <&hdmi_ctl>; + #sound-dai-cells = <0>; status = "disabled"; ports { diff --git a/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts b/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts index 06790f05b395..4de9a45c4883 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rockchip/rk3066a-mk808.dts @@ -143,6 +143,14 @@ }; }; +&hdmi_sound { + status = "okay"; +}; + +&i2s0 { + status = "okay"; +}; + &mmc0 { bus-width = <4>; cap-mmc-highspeed; diff --git a/arch/arm/boot/dts/rockchip/rk3066a.dtsi b/arch/arm/boot/dts/rockchip/rk3066a.dtsi index 15cbd94d7ec0..3f6d49459734 100644 --- a/arch/arm/boot/dts/rockchip/rk3066a.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3066a.dtsi @@ -53,6 +53,22 @@ ports = <&vop0_out>, <&vop1_out>; }; + hdmi_sound: hdmi-sound { + compatible = "simple-audio-card"; + simple-audio-card,name = "HDMI"; + simple-audio-card,format = "i2s"; + simple-audio-card,mclk-fs = <256>; + status = "disabled"; + + simple-audio-card,codec { + sound-dai = <&hdmi>; + }; + + simple-audio-card,cpu { + sound-dai = <&i2s0>; + }; + }; + sram: sram@10080000 { compatible = "mmio-sram"; reg = <0x10080000 0x10000>; @@ -880,7 +896,3 @@ &wdt { compatible = "rockchip,rk3066-wdt", "snps,dw-wdt"; }; - -&emac { - compatible = "rockchip,rk3066-emac"; -}; diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index fb98873fd94e..23e633387c24 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -216,6 +216,8 @@ <&cru ACLK_LCDC0>, <&cru HCLK_LCDC0>, <&cru PCLK_MIPI>, + <&cru PCLK_MIPIPHY>, + <&cru SCLK_MIPI_24M>, <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru ACLK_VIO0>, @@ -275,6 +277,43 @@ reg = <0>; remote-endpoint = <&hdmi_in_vop>; }; + + vop_out_dsi: endpoint@1 { + reg = <1>; + remote-endpoint = <&dsi_in_vop>; + }; + }; + }; + + dsi: dsi@10110000 { + compatible = "rockchip,rk3128-mipi-dsi", "snps,dw-mipi-dsi"; + reg = <0x10110000 0x4000>; + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_MIPI>; + clock-names = "pclk"; + phys = <&dphy>; + phy-names = "dphy"; + power-domains = <&power RK3128_PD_VIO>; + resets = <&cru SRST_VIO_MIPI_DSI>; + reset-names = "apb"; + rockchip,grf = <&grf>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + dsi_in: port@0 { + reg = <0>; + + dsi_in_vop: endpoint { + remote-endpoint = <&vop_out_dsi>; + }; + }; + + dsi_out: port@1 { + reg = <1>; + }; }; }; @@ -360,6 +399,41 @@ status = "disabled"; }; + i2s_8ch: i2s@10200000 { + compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; + reg = <0x10200000 0x1000>; + interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S_8CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&pdma 14>, <&pdma 15>; + dma-names = "tx", "rx"; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + spdif: spdif@10204000 { + compatible = "rockchip,rk3128-spdif", "rockchip,rk3066-spdif"; + reg = <0x10204000 0x1000>; + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF>; + clock-names = "mclk", "hclk"; + dmas = <&pdma 13>; + dma-names = "tx"; + pinctrl-names = "default"; + pinctrl-0 = <&spdif_tx>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + + sfc: spi@1020c000 { + compatible = "rockchip,sfc"; + reg = <0x1020c000 0x8000>; + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_SFC>, <&cru 479>; + clock-names = "clk_sfc", "hclk_sfc"; + status = "disabled"; + }; + sdmmc: mmc@10214000 { compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; reg = <0x10214000 0x4000>; @@ -408,6 +482,21 @@ status = "disabled"; }; + i2s_2ch: i2s@10220000 { + compatible = "rockchip,rk3128-i2s", "rockchip,rk3066-i2s"; + reg = <0x10220000 0x1000>; + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S_2CH>; + clock-names = "i2s_clk", "i2s_hclk"; + dmas = <&pdma 0>, <&pdma 1>; + dma-names = "tx", "rx"; + rockchip,playback-channels = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2s_bus>; + #sound-dai-cells = <0>; + status = "disabled"; + }; + nfc: nand-controller@10500000 { compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; reg = <0x10500000 0x4000>; @@ -477,6 +566,7 @@ pinctrl-names = "default"; pinctrl-0 = <&hdmii2c_xfer &hdmi_hpd &hdmi_cec>; power-domains = <&power RK3128_PD_VIO>; + #sound-dai-cells = <0>; status = "disabled"; ports { @@ -496,6 +586,18 @@ }; }; + dphy: phy@20038000 { + compatible = "rockchip,rk3128-dsi-dphy"; + reg = <0x20038000 0x4000>; + clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPIPHY>; + clock-names = "ref", "pclk"; + #phy-cells = <0>; + power-domains = <&power RK3128_PD_VIO>; + resets = <&cru SRST_MIPIPHY_P>; + reset-names = "apb"; + status = "disabled"; + }; + timer0: timer@20044000 { compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; reg = <0x20044000 0x20>; @@ -1104,6 +1206,32 @@ }; }; + sfc { + sfc_bus2: sfc-bus2 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>; + }; + + sfc_bus4: sfc-bus4 { + rockchip,pins = <1 RK_PD0 3 &pcfg_pull_default>, + <1 RK_PD1 3 &pcfg_pull_default>, + <1 RK_PD2 3 &pcfg_pull_default>, + <1 RK_PD3 3 &pcfg_pull_default>; + }; + + sfc_clk: sfc-clk { + rockchip,pins = <2 RK_PA4 3 &pcfg_pull_none>; + }; + + sfc_cs0: sfc-cs0 { + rockchip,pins = <2 RK_PA2 2 &pcfg_pull_default>; + }; + + sfc_cs1: sfc-cs1 { + rockchip,pins = <2 RK_PA3 2 &pcfg_pull_default>; + }; + }; + spdif { spdif_tx: spdif-tx { rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; diff --git a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi index f37137f298d5..e6a78bcf9163 100644 --- a/arch/arm/boot/dts/rockchip/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3xxx.dtsi @@ -194,17 +194,14 @@ }; emac: ethernet@10204000 { - compatible = "snps,arc-emac"; + compatible = "rockchip,rk3066-emac"; reg = <0x10204000 0x3c>; interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; - - rockchip,grf = <&grf>; - clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; clock-names = "hclk", "macref"; max-speed = <100>; phy-mode = "rmii"; - + rockchip,grf = <&grf>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts index 0c2396b8f8db..7707d1b01440 100644 --- a/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts +++ b/arch/arm/boot/dts/rockchip/rv1126-edgeble-neu2-io.dts @@ -69,8 +69,7 @@ &mdio { phy: ethernet-phy@0 { - compatible = "ethernet-phy-id001c.c916", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id001c.c916"; reg = <0x0>; pinctrl-names = "default"; pinctrl-0 = <ð_phy_rst>; diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index 9fedd6776208..015903d09323 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ stm32h750i-art-pi.dtb \ + stm32mp135f-dhcor-dhsbc.dtb \ stm32mp135f-dk.dtb \ stm32mp151a-prtt1a.dtb \ stm32mp151a-prtt1c.dtb \ diff --git a/arch/arm/boot/dts/st/stih407-family.dtsi b/arch/arm/boot/dts/st/stih407-family.dtsi index 29302e74aa1d..35a55aef7f4b 100644 --- a/arch/arm/boot/dts/st/stih407-family.dtsi +++ b/arch/arm/boot/dts/st/stih407-family.dtsi @@ -33,7 +33,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; - cpu@0 { + cpu0: cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; @@ -52,8 +52,9 @@ clock-latency = <100000>; cpu0-supply = <&pwm_regulator>; st,syscfg = <&syscfg_core 0x8e0>; + #cooling-cells = <2>; }; - cpu@1 { + cpu1: cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; @@ -66,6 +67,7 @@ 1200000 0 800000 0 500000 0>; + #cooling-cells = <2>; }; }; diff --git a/arch/arm/boot/dts/st/stih410.dtsi b/arch/arm/boot/dts/st/stih410.dtsi index 29e95e9d3229..a69231854f78 100644 --- a/arch/arm/boot/dts/st/stih410.dtsi +++ b/arch/arm/boot/dts/st/stih410.dtsi @@ -270,6 +270,7 @@ clock-names = "thermal"; clocks = <&clk_sysin>; interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; }; cec@94a087c { diff --git a/arch/arm/boot/dts/st/stih418.dtsi b/arch/arm/boot/dts/st/stih418.dtsi index b35b9b7a7ccc..8fb8b3af5e49 100644 --- a/arch/arm/boot/dts/st/stih418.dtsi +++ b/arch/arm/boot/dts/st/stih418.dtsi @@ -6,23 +6,26 @@ #include "stih418-clock.dtsi" #include "stih407-family.dtsi" #include "stih410-pinctrl.dtsi" +#include <dt-bindings/thermal/thermal.h> / { cpus { #address-cells = <1>; #size-cells = <0>; - cpu@2 { + cpu2: cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + #cooling-cells = <2>; }; - cpu@3 { + cpu3: cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; /* u-boot puts hpen in SBC dmem at 0xa4 offset */ cpu-release-addr = <0x94100A4>; + #cooling-cells = <2>; }; }; @@ -44,6 +47,38 @@ reset-names = "global", "port"; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <250>; /* 250ms */ + polling-delay = <1000>; /* 1000ms */ + + thermal-sensors = <&thermal>; + + trips { + cpu_crit: cpu-crit { + temperature = <95000>; /* 95C */ + hysteresis = <2000>; + type = "critical"; + }; + cpu_alert: cpu-alert { + temperature = <85000>; /* 85C */ + hysteresis = <2000>; + type = "passive"; + }; + }; + + cooling-maps { + map { + trip = <&cpu_alert>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + soc { rng11: rng@8a8a000 { status = "disabled"; @@ -107,12 +142,13 @@ assigned-clock-rates = <200000000>; }; - thermal@91a0000 { + thermal: thermal@91a0000 { compatible = "st,stih407-thermal"; reg = <0x91a0000 0x28>; clock-names = "thermal"; clocks = <&clk_sysin>; interrupts = <GIC_SPI 205 IRQ_TYPE_EDGE_RISING>; + #thermal-sensor-cells = <0>; }; }; }; diff --git a/arch/arm/boot/dts/st/stm32f429.dtsi b/arch/arm/boot/dts/st/stm32f429.dtsi index 8efcda9ef8ae..ad91b74ddd0d 100644 --- a/arch/arm/boot/dts/st/stm32f429.dtsi +++ b/arch/arm/boot/dts/st/stm32f429.dtsi @@ -579,6 +579,7 @@ syscfg: syscon@40013800 { compatible = "st,stm32-syscfg", "syscon"; reg = <0x40013800 0x400>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SYSCFG)>; }; exti: interrupt-controller@40013c00 { diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 32c5d8a1e06a..c9f588a65094 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -6,6 +6,14 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + /omit-if-no-ref/ + adc1_pins_a: adc1-pins-0 { + pins { + pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* ADC1 in12 */ + }; + }; + + /omit-if-no-ref/ adc1_usb_cc_pins_a: adc1-usb-cc-pins-0 { pins { pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ @@ -13,6 +21,241 @@ }; }; + /omit-if-no-ref/ + adc1_usb_cc_pins_b: adc1-usb-cc-pins-1 { + pins { + pinmux = <STM32_PINMUX('A', 5, ANALOG)>, /* ADC1_INP2 */ + <STM32_PINMUX('F', 13, ANALOG)>; /* ADC1_INP11 */ + }; + }; + + /omit-if-no-ref/ + dcmipp_pins_a: dcmi-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ + <STM32_PINMUX('G', 9, AF13)>,/* DCMI_VSYNC */ + <STM32_PINMUX('B', 7, AF14)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, AF13)>,/* DCMI_D0 */ + <STM32_PINMUX('D', 0, AF13)>,/* DCMI_D1 */ + <STM32_PINMUX('G', 10, AF13)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 4, AF13)>,/* DCMI_D3 */ + <STM32_PINMUX('D', 11, AF14)>,/* DCMI_D4 */ + <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ + <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 14, AF13)>;/* DCMI_D7 */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + dcmipp_sleep_pins_a: dcmi-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ + <STM32_PINMUX('G', 9, ANALOG)>,/* DCMI_VSYNC */ + <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_PIXCLK */ + <STM32_PINMUX('A', 9, ANALOG)>,/* DCMI_D0 */ + <STM32_PINMUX('D', 0, ANALOG)>,/* DCMI_D1 */ + <STM32_PINMUX('G', 10, ANALOG)>,/* DCMI_D2 */ + <STM32_PINMUX('E', 4, ANALOG)>,/* DCMI_D3 */ + <STM32_PINMUX('D', 11, ANALOG)>,/* DCMI_D4 */ + <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ + <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ + <STM32_PINMUX('E', 14, ANALOG)>;/* DCMI_D7 */ + }; + }; + + /omit-if-no-ref/ + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 5, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, AF11)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 7, AF11)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('D', 7, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 5, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('A', 7, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('D', 7, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + /omit-if-no-ref/ + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH_RMII_TXD0 */ + <STM32_PINMUX('G', 14, AF11)>, /* ETH_RMII_TXD1 */ + <STM32_PINMUX('B', 11, AF11)>, /* ETH_RMII_TX_EN */ + <STM32_PINMUX('A', 1, AF11)>, /* ETH_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 2, AF11)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RMII_RXD0 */ + <STM32_PINMUX('C', 5, AF11)>, /* ETH_RMII_RXD1 */ + <STM32_PINMUX('C', 1, AF10)>; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RMII_TXD0 */ + <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RMII_TXD1 */ + <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RMII_TX_EN */ + <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RMII_REF_CLK */ + <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 2, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RMII_RXD0 */ + <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RMII_RXD1 */ + <STM32_PINMUX('C', 1, ANALOG)>; /* ETH_RMII_CRS_DV */ + }; + }; + + /omit-if-no-ref/ + eth2_rgmii_pins_a: eth2-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 11, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('G', 1, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 6, AF11)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('F', 6, AF11)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('G', 3, AF10)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 6, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('E', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, AF12)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('A', 8, AF11)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 12, AF11)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('H', 11, AF11)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + eth2_rgmii_sleep_pins_a: eth2-rgmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('G', 1, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('E', 6, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('G', 3, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('B', 6, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('A', 8, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 12, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('H', 11, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + /omit-if-no-ref/ + eth2_rmii_pins_a: eth2-rmii-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH_RMII_TXD0 */ + <STM32_PINMUX('G', 11, AF10)>, /* ETH_RMII_TXD1 */ + <STM32_PINMUX('G', 8, AF13)>, /* ETH_RMII_ETHCK */ + <STM32_PINMUX('F', 6, AF11)>, /* ETH_RMII_TX_EN */ + <STM32_PINMUX('B', 2, AF11)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 5, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH_RMII_RXD0 */ + <STM32_PINMUX('E', 2, AF10)>, /* ETH_RMII_RXD1 */ + <STM32_PINMUX('A', 12, AF11)>; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH_RMII_TXD0 */ + <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RMII_TXD1 */ + <STM32_PINMUX('G', 8, ANALOG)>, /* ETH_RMII_ETHCK */ + <STM32_PINMUX('F', 6, ANALOG)>, /* ETH_RMII_TX_EN */ + <STM32_PINMUX('B', 2, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('F', 4, ANALOG)>, /* ETH_RMII_RXD0 */ + <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RMII_RXD1 */ + <STM32_PINMUX('A', 12, ANALOG)>; /* ETH_RMII_CRS_DV */ + }; + }; + + /omit-if-no-ref/ + goodix_pins_a: goodix-0 { + /* + * touchscreen reset needs to be configured + * via the pinctrl not the driver (a pull-down resistor + * has been soldered onto the reset line which forces + * the touchscreen to reset state). + */ + pins1 { + pinmux = <STM32_PINMUX('H', 2, GPIO)>; + output-high; + bias-pull-up; + }; + /* + * Interrupt line must have a pull-down resistor + * in order to freeze the i2c address at 0x5D + */ + pins2 { + pinmux = <STM32_PINMUX('F', 5, GPIO)>; + bias-pull-down; + }; + }; + + /omit-if-no-ref/ i2c1_pins_a: i2c1-0 { pins { pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ @@ -23,6 +266,7 @@ }; }; + /omit-if-no-ref/ i2c1_sleep_pins_a: i2c1-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ @@ -30,6 +274,7 @@ }; }; + /omit-if-no-ref/ i2c5_pins_a: i2c5-0 { pins { pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ @@ -40,6 +285,7 @@ }; }; + /omit-if-no-ref/ i2c5_sleep_pins_a: i2c5-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ @@ -47,6 +293,26 @@ }; }; + /omit-if-no-ref/ + i2c5_pins_b: i2c5-1 { + pins { + pinmux = <STM32_PINMUX('D', 1, AF4)>, /* I2C5_SCL */ + <STM32_PINMUX('E', 13, AF4)>; /* I2C5_SDA */ + bias-disable; + drive-open-drain; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + i2c5_sleep_pins_b: i2c5-sleep-1 { + pins { + pinmux = <STM32_PINMUX('D', 1, ANALOG)>, /* I2C5_SCL */ + <STM32_PINMUX('E', 13, ANALOG)>; /* I2C5_SDA */ + }; + }; + + /omit-if-no-ref/ ltdc_pins_a: ltdc-0 { pins { pinmux = <STM32_PINMUX('D', 9, AF13)>, /* LCD_CLK */ @@ -77,6 +343,7 @@ }; }; + /omit-if-no-ref/ ltdc_sleep_pins_a: ltdc-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_CLK */ @@ -104,6 +371,51 @@ }; }; + /omit-if-no-ref/ + m_can1_pins_a: m-can1-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 10, AF9)>; /* CAN1_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 0, AF9)>; /* CAN1_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + m_can1_sleep_pins_a: m_can1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 10, ANALOG)>, /* CAN1_TX */ + <STM32_PINMUX('D', 0, ANALOG)>; /* CAN1_RX */ + }; + }; + + /omit-if-no-ref/ + m_can2_pins_a: m-can2-0 { + pins1 { + pinmux = <STM32_PINMUX('G', 0, AF9)>; /* CAN2_TX */ + slew-rate = <1>; + drive-push-pull; + bias-disable; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 0, AF9)>; /* CAN2_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + m_can2_sleep_pins_a: m_can2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('G', 0, ANALOG)>, /* CAN2_TX */ + <STM32_PINMUX('E', 0, ANALOG)>; /* CAN2_RX */ + }; + }; + + /omit-if-no-ref/ mcp23017_pins_a: mcp23017-0 { pins { pinmux = <STM32_PINMUX('G', 12, GPIO)>; @@ -111,6 +423,7 @@ }; }; + /omit-if-no-ref/ pwm3_pins_a: pwm3-0 { pins { pinmux = <STM32_PINMUX('B', 1, AF2)>; /* TIM3_CH4 */ @@ -120,12 +433,14 @@ }; }; + /omit-if-no-ref/ pwm3_sleep_pins_a: pwm3-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 1, ANALOG)>; /* TIM3_CH4 */ }; }; + /omit-if-no-ref/ pwm4_pins_a: pwm4-0 { pins { pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ @@ -135,12 +450,31 @@ }; }; + /omit-if-no-ref/ pwm4_sleep_pins_a: pwm4-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ }; }; + /omit-if-no-ref/ + pwm5_pins_a: pwm5-0 { + pins { + pinmux = <STM32_PINMUX('H', 12, AF2)>; /* TIM5_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + pwm5_sleep_pins_a: pwm5-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 12, ANALOG)>; /* TIM5_CH3 */ + }; + }; + + /omit-if-no-ref/ pwm8_pins_a: pwm8-0 { pins { pinmux = <STM32_PINMUX('E', 5, AF3)>; /* TIM8_CH3 */ @@ -150,12 +484,31 @@ }; }; + /omit-if-no-ref/ pwm8_sleep_pins_a: pwm8-sleep-0 { pins { pinmux = <STM32_PINMUX('E', 5, ANALOG)>; /* TIM8_CH3 */ }; }; + /omit-if-no-ref/ + pwm13_pins_a: pwm13-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, AF9)>; /* TIM13_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + /omit-if-no-ref/ + pwm13_sleep_pins_a: pwm13-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 6, ANALOG)>; /* TIM13_CH1 */ + }; + }; + + /omit-if-no-ref/ pwm14_pins_a: pwm14-0 { pins { pinmux = <STM32_PINMUX('F', 9, AF9)>; /* TIM14_CH1 */ @@ -165,12 +518,107 @@ }; }; + /omit-if-no-ref/ pwm14_sleep_pins_a: pwm14-sleep-0 { pins { pinmux = <STM32_PINMUX('F', 9, ANALOG)>; /* TIM14_CH1 */ }; }; + /omit-if-no-ref/ + qspi_clk_pins_a: qspi-clk-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + }; + + /omit-if-no-ref/ + qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ + }; + }; + + /omit-if-no-ref/ + qspi_bk1_pins_a: qspi-bk1-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('D', 11, AF9)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('H', 7, AF13)>; /* QSPI_BK1_IO3 */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + }; + + /omit-if-no-ref/ + qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ + <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ + <STM32_PINMUX('D', 11, ANALOG)>, /* QSPI_BK1_IO2 */ + <STM32_PINMUX('H', 7, ANALOG)>; /* QSPI_BK1_IO3 */ + }; + }; + + /omit-if-no-ref/ + qspi_cs1_pins_a: qspi-cs1-0 { + pins { + pinmux = <STM32_PINMUX('B', 2, AF9)>; /* QSPI_BK1_NCS */ + bias-pull-up; + drive-push-pull; + slew-rate = <1>; + }; + }; + + /omit-if-no-ref/ + qspi_cs1_sleep_pins_a: qspi-cs1-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 2, ANALOG)>; /* QSPI_BK1_NCS */ + }; + }; + + /omit-if-no-ref/ + sai1a_pins_a: sai1a-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, AF12)>, /* SAI1_SCK_A */ + <STM32_PINMUX('D', 6, AF6)>, /* SAI1_SD_A */ + <STM32_PINMUX('E', 11, AF6)>; /* SAI1_FS_A */ + slew-rate = <0>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + sai1a_sleep_pins_a: sai1a-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* SAI1_SCK_A */ + <STM32_PINMUX('D', 6, ANALOG)>, /* SAI1_SD_A */ + <STM32_PINMUX('E', 11, ANALOG)>; /* SAI1_FS_A */ + }; + }; + + /omit-if-no-ref/ + sai1b_pins_a: sai1b-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, AF6)>; /* SAI1_SD_B */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + sai1b_sleep_pins_a: sai1b-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 0, ANALOG)>; /* SAI1_SD_B */ + }; + }; + + /omit-if-no-ref/ sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -184,6 +632,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { pins1 { pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ @@ -202,6 +651,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { pins { pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ @@ -213,6 +663,7 @@ }; }; + /omit-if-no-ref/ sdmmc1_clk_pins_a: sdmmc1-clk-0 { pins { pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ @@ -222,6 +673,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_pins_a: sdmmc2-b4-0 { pins { pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ @@ -235,6 +687,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { pins1 { pinmux = <STM32_PINMUX('B', 14, AF10)>, /* SDMMC2_D0 */ @@ -253,6 +706,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { pins { pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ @@ -264,6 +718,7 @@ }; }; + /omit-if-no-ref/ sdmmc2_clk_pins_a: sdmmc2-clk-0 { pins { pinmux = <STM32_PINMUX('E', 3, AF10)>; /* SDMMC2_CK */ @@ -273,6 +728,80 @@ }; }; + /omit-if-no-ref/ + sdmmc2_d47_pins_a: sdmmc2-d47-0 { + pins { + pinmux = <STM32_PINMUX('F', 0, AF10)>, /* SDMMC2_D4 */ + <STM32_PINMUX('B', 9, AF10)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ + slew-rate = <1>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { + pins { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC2_D4 */ + <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC2_D5 */ + <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ + <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ + }; + }; + + /omit-if-no-ref/ + spi2_pins_a: spi2-0 { + pins1 { + pinmux = <STM32_PINMUX('B', 10, AF6)>, /* SPI2_SCK */ + <STM32_PINMUX('H', 10, AF6)>; /* SPI2_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('B', 5, AF5)>; /* SPI2_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi2_sleep_pins_a: spi2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* SPI2_SCK */ + <STM32_PINMUX('B', 5, ANALOG)>, /* SPI2_MISO */ + <STM32_PINMUX('H', 10, ANALOG)>; /* SPI2_MOSI */ + }; + }; + + /omit-if-no-ref/ + spi3_pins_a: spi3-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 13, AF6)>, /* SPI3_SCK */ + <STM32_PINMUX('F', 1, AF5)>; /* SPI3_MOSI */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = <STM32_PINMUX('D', 4, AF5)>; /* SPI3_MISO */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + spi3_sleep_pins_a: spi3-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* SPI3_SCK */ + <STM32_PINMUX('D', 4, ANALOG)>, /* SPI3_MISO */ + <STM32_PINMUX('F', 1, ANALOG)>; /* SPI3_MOSI */ + }; + }; + + /omit-if-no-ref/ spi5_pins_a: spi5-0 { pins1 { pinmux = <STM32_PINMUX('H', 7, AF6)>, /* SPI5_SCK */ @@ -288,6 +817,7 @@ }; }; + /omit-if-no-ref/ spi5_sleep_pins_a: spi5-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 7, ANALOG)>, /* SPI5_SCK */ @@ -296,6 +826,7 @@ }; }; + /omit-if-no-ref/ stm32g0_intn_pins_a: stm32g0-intn-0 { pins { pinmux = <STM32_PINMUX('I', 2, GPIO)>; @@ -303,6 +834,7 @@ }; }; + /omit-if-no-ref/ uart4_pins_a: uart4-0 { pins1 { pinmux = <STM32_PINMUX('D', 6, AF8)>; /* UART4_TX */ @@ -316,6 +848,7 @@ }; }; + /omit-if-no-ref/ uart4_idle_pins_a: uart4-idle-0 { pins1 { pinmux = <STM32_PINMUX('D', 6, ANALOG)>; /* UART4_TX */ @@ -326,6 +859,7 @@ }; }; + /omit-if-no-ref/ uart4_sleep_pins_a: uart4-sleep-0 { pins { pinmux = <STM32_PINMUX('D', 6, ANALOG)>, /* UART4_TX */ @@ -333,6 +867,84 @@ }; }; + /omit-if-no-ref/ + uart4_pins_b: uart4-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, AF8)>; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_b: uart4-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>; /* UART4_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 8, AF8)>; /* UART4_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + uart4_sleep_pins_b: uart4-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 9, ANALOG)>, /* UART4_TX */ + <STM32_PINMUX('D', 8, ANALOG)>; /* UART4_RX */ + }; + }; + + /omit-if-no-ref/ + uart7_pins_a: uart7-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 2, AF8)>, /* UART7_TX */ + <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('E', 10, AF7)>, /* UART7_RX */ + <STM32_PINMUX('G', 7, AF8)>; /* UART7_CTS_NSS */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart7_idle_pins_a: uart7-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('B', 12, AF7)>; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('E', 10, AF7)>; /* UART7_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart7_sleep_pins_a: uart7-sleep-0 { + pins { + pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* UART7_TX */ + <STM32_PINMUX('B', 12, ANALOG)>, /* UART7_RTS */ + <STM32_PINMUX('E', 10, ANALOG)>, /* UART7_RX */ + <STM32_PINMUX('G', 7, ANALOG)>; /* UART7_CTS_NSS */ + }; + }; + + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ @@ -346,6 +958,7 @@ }; }; + /omit-if-no-ref/ uart8_idle_pins_a: uart8-idle-0 { pins1 { pinmux = <STM32_PINMUX('E', 1, ANALOG)>; /* UART8_TX */ @@ -356,6 +969,7 @@ }; }; + /omit-if-no-ref/ uart8_sleep_pins_a: uart8-sleep-0 { pins { pinmux = <STM32_PINMUX('E', 1, ANALOG)>, /* UART8_TX */ @@ -363,6 +977,7 @@ }; }; + /omit-if-no-ref/ usart1_pins_a: usart1-0 { pins1 { pinmux = <STM32_PINMUX('C', 0, AF7)>, /* USART1_TX */ @@ -378,6 +993,7 @@ }; }; + /omit-if-no-ref/ usart1_idle_pins_a: usart1-idle-0 { pins1 { pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ @@ -395,6 +1011,7 @@ }; }; + /omit-if-no-ref/ usart1_sleep_pins_a: usart1-sleep-0 { pins { pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ @@ -404,6 +1021,40 @@ }; }; + /omit-if-no-ref/ + usart1_pins_b: usart1-1 { + pins1 { + pinmux = <STM32_PINMUX('C', 0, AF7)>; /* USART1_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + usart1_idle_pins_b: usart1-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>; /* USART1_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('D', 14, AF7)>; /* USART1_RX */ + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + usart1_sleep_pins_b: usart1-sleep-1 { + pins { + pinmux = <STM32_PINMUX('C', 0, ANALOG)>, /* USART1_TX */ + <STM32_PINMUX('D', 14, ANALOG)>; /* USART1_RX */ + }; + }; + + /omit-if-no-ref/ usart2_pins_a: usart2-0 { pins1 { pinmux = <STM32_PINMUX('H', 12, AF1)>, /* USART2_TX */ @@ -419,6 +1070,7 @@ }; }; + /omit-if-no-ref/ usart2_idle_pins_a: usart2-idle-0 { pins1 { pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ @@ -436,6 +1088,7 @@ }; }; + /omit-if-no-ref/ usart2_sleep_pins_a: usart2-sleep-0 { pins { pinmux = <STM32_PINMUX('H', 12, ANALOG)>, /* USART2_TX */ @@ -444,4 +1097,48 @@ <STM32_PINMUX('E', 11, ANALOG)>; /* USART2_CTS_NSS */ }; }; + + /omit-if-no-ref/ + usart2_pins_b: usart2-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 11, AF1)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('D', 15, AF1)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, AF3)>; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart2_idle_pins_b: usart2-idle-1 { + pins1 { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = <STM32_PINMUX('D', 15, AF1)>; /* USART2_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + usart2_sleep_pins_b: usart2-sleep-1 { + pins { + pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ + <STM32_PINMUX('D', 15, ANALOG)>, /* USART2_RX */ + <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ + }; + }; }; diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index 6704ceef284d..e1a764d269d2 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -979,6 +979,12 @@ ts_cal2: calib@5e { reg = <0x5e 0x2>; }; + ethernet_mac1_address: mac1@e4 { + reg = <0xe4 0x6>; + }; + ethernet_mac2_address: mac2@ea { + reg = <0xea 0x6>; + }; }; etzpc: bus@5c007000 { @@ -1505,6 +1511,38 @@ status = "disabled"; }; + ethernet1: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + access-controllers = <&etzpc 48>; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; + usbphyc: usbphyc@5a006000 { #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index 3e394c8e58b9..73e470019ce4 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -68,4 +68,35 @@ }; }; }; + + ethernet2: ethernet@5800e000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800e000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH2MAC>, + <&rcc ETH2TX>, + <&rcc ETH2RX>, + <&rcc ETH2STP>, + <&rcc ETH2CK_K>; + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + access-controllers = <&etzpc 49>; + status = "disabled"; + + stmmac_axi_config_2: stmmac-axi-config { + snps,blen = <0 0 0 0 16 8 4>; + snps,rd_osr_lmt = <0x7>; + snps,wr_osr_lmt = <0x7>; + }; + }; }; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts new file mode 100644 index 000000000000..bacb70b4256b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp135f-dhcor-dhsbc.dts @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + * + * DHCOR STM32MP13 variant: + * DHCR-STM32MP135F-C100-R051-EE-F0409-SPI4-RTC-WBT-I-01LG + * DHCOR PCB number: 718-100 or newer + * DHSBC PCB number: 719-100 or newer + */ + +/dts-v1/; + +#include <dt-bindings/regulator/st,stm32mp13-regulator.h> +#include "stm32mp135.dtsi" +#include "stm32mp13xf.dtsi" +#include "stm32mp13xx-dhcor-som.dtsi" + +/ { + model = "DH electronics STM32MP135F DHCOR DHSBC"; + compatible = "dh,stm32mp135f-dhcor-dhsbc", + "dh,stm32mp135f-dhcor-som", + "st,stm32mp135"; + + aliases { + ethernet0 = ðernet1; + ethernet1 = ðernet2; + serial2 = &usart1; + serial3 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc_1 { + pinctrl-names = "default"; + pinctrl-0 = <&adc1_pins_a &adc1_usb_cc_pins_b>; + vdda-supply = <&vdd_adc>; + vref-supply = <&vdd_adc>; + status = "okay"; + + adc1: adc@0 { + status = "okay"; + + /* + * Type-C USB_PWR_CC1 & USB_PWR_CC2 on in2 & in11. + * Use at least 5 * RC time, e.g. 5 * (Rp + Rd) * C: + * 5 * (5.1 + 47kOhms) * 5pF => 1.3us. + * Use arbitrary margin here (e.g. 5us). + * + * The pinmux pins must be set as ANALOG, use datasheet + * DS13483 Table 7. STM32MP135C/F ball definitions to + * find out which 'pin name' maps to which 'additional + * functions', which lists the mapping between pin and + * ADC channel. In this case, PA5 maps to ADC1_INP2 and + * PF13 maps to ADC1_INP11 . + */ + channel@2 { + reg = <2>; + st,min-sample-time-ns = <5000>; + }; + + channel@11 { + reg = <11>; + st,min-sample-time-ns = <5000>; + }; + + /* Expansion connector: INP12:pin29 */ + channel@12 { + reg = <12>; + st,min-sample-time-ns = <5000>; + }; + }; +}; + +ðernet1 { + phy-handle = <ðphy1>; + phy-mode = "rgmii-id"; + pinctrl-0 = <ð1_rgmii_pins_a>; + pinctrl-1 = <ð1_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy1: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + interrupt-parent = <&gpiog>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&gpioa 11 GPIO_ACTIVE_LOW>; + }; + }; +}; + +ðernet2 { + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + pinctrl-0 = <ð2_rgmii_pins_a>; + pinctrl-1 = <ð2_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + ethphy2: ethernet-phy@1 { + /* RTL8211F */ + compatible = "ethernet-phy-id001c.c916"; + interrupt-parent = <&gpiog>; + interrupts = <15 IRQ_TYPE_LEVEL_LOW>; + reg = <1>; + reset-assert-us = <15000>; + reset-deassert-us = <55000>; + reset-gpios = <&gpiog 8 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&gpioa { + gpio-line-names = "", "", "", "", + "", "DHSBC_USB_PWR_CC1", "", "", + "", "", "", "DHSBC_nETH1_RST", + "", "DHCOR_HW-CODING_0", "", ""; +}; + +&gpiob { + gpio-line-names = "", "", "", "", + "", "", "", "DHCOR_BT_HOST_WAKE", + "", "", "", "", + "", "DHSBC_nTPM_CS", "", ""; +}; + +&gpioc { + gpio-line-names = "", "", "", "DHSBC_USB_5V_MEAS", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "DHCOR_RAM-CODING_0", "", "", + "", "DHCOR_RAM-CODING_1", "", "", + "", "", "", ""; +}; + +&gpioe { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "DHSBC_nTPM_RST", "", "", + "DHSBC_nTPM_PIRQ", "", "DHCOR_WL_HOST_WAKE", ""; +}; + +&gpiof { + gpio-line-names = "", "", "DHSBC_USB_PWR_nFLT", "", + "", "", "", "", + "", "", "", "", + "DHCOR_WL_REG_ON", "DHSBC_USB_PWR_CC2", "", ""; +}; + +&gpiog { + gpio-line-names = "", "", "", "", + "", "", "", "", + "DHSBC_nETH2_RST", "DHCOR_BT_DEV_WAKE", "", "", + "DHSBC_ETH1_INTB", "", "", "DHSBC_ETH2_INTB"; +}; + +&gpioi { + gpio-line-names = "DHCOR_RTC_nINT", "DHCOR_HW-CODING_1", + "DHCOR_BT_REG_ON", "DHCOR_PMIC_nINT", + "DHSBC_BOOT0", "DHSBC_BOOT1", + "DHSBC_BOOT2", "DHSBC_USB-C_DATA_VBUS"; +}; + +&i2c1 { /* Expansion connector: SDA:pin27 SCL:pin28 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&i2c5 { /* Expansion connector: SDA:pin3 SCL:pin5 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c5_pins_b>; + pinctrl-1 = <&i2c5_sleep_pins_b>; + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&m_can1 { /* Expansion connector: TX:pin16 RX:pin18 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { /* Expansion connector: TX:pin22 RX:pin26 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; + status = "okay"; +}; + +&sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */ + clocks = <&rcc SAI1>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names = "pclk", "x8k", "x11k"; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sai1a_pins_a &sai1b_pins_a>; + pinctrl-1 = <&sai1a_sleep_pins_a &sai1b_sleep_pins_a>; +}; + +&scmi_voltd { + status = "disabled"; +}; + +&spi2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi2_pins_a>; + pinctrl-1 = <&spi2_sleep_pins_a>; + cs-gpios = <&gpiob 13 0>; + status = "okay"; + + st33htph: tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <24000000>; + }; +}; + +&spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */ + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi3_pins_a>; + pinctrl-1 = <&spi3_sleep_pins_a>; + cs-gpios = <&gpiof 3 0>; + status = "disabled"; +}; + +&timers5 { /* Expansion connector: CH3:pin31 */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm5_pins_a>; + pinctrl-1 = <&pwm5_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@4 { + status = "okay"; + }; +}; + +&timers13 { /* Expansion connector: CH1:pin32 */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + pwm { + pinctrl-0 = <&pwm13_pins_a>; + pinctrl-1 = <&pwm13_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@12 { + status = "okay"; + }; +}; + +&usart1 { /* Expansion connector: RX:pin33 TX:pin37 */ + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart1_pins_b>; + pinctrl-1 = <&usart1_sleep_pins_b>; + pinctrl-2 = <&usart1_idle_pins_b>; + status = "okay"; +}; + +&usart2 { /* Expansion connector: RX:pin10 TX:pin8 RTS:pin11 CTS:pin36 */ + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_b>; + pinctrl-1 = <&usart2_sleep_pins_b>; + pinctrl-2 = <&usart2_idle_pins_b>; + uart-has-rtscts; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbh_ohci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbotg_hs { + dr_mode = "peripheral"; + phys = <&usbphyc_port1 0>; + phy-names = "usb2-phy"; + usb33d-supply = <&usb33>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + connector { + compatible = "usb-a-connector"; + vbus-supply = <&vbus_sw>; + }; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; + st,current-boost-microamp = <1000>; + st,decrease-hs-slew-rate; + st,tune-hs-dc-level = <2>; + st,enable-hs-rftime-reduction; + st,trim-hs-current = <11>; + st,trim-hs-impedance = <2>; + st,tune-squelch-level = <1>; + st,enable-hs-rx-gain-eq; + st,no-hs-ftime-ctrl; + st,no-lsfs-sc; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + vbus-gpios = <&gpioi 7 GPIO_ACTIVE_HIGH>; + label = "Type-C"; + self-powered; + type = "micro"; + }; +}; diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index 567e53ad285f..1af335a39993 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -19,6 +19,7 @@ compatible = "st,stm32mp135f-dk", "st,stm32mp135"; aliases { + ethernet0 = ðernet1; serial0 = &uart4; serial1 = &usart1; serial2 = &uart8; @@ -29,6 +30,20 @@ stdout-path = "serial0:115200n8"; }; + clocks { + clk_ext_camera: clk-ext-camera { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_mco1: clk-mco1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + memory@c0000000 { device_type = "memory"; reg = <0xc0000000 0x20000000>; @@ -141,6 +156,45 @@ status = "okay"; }; +&dcmipp { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&dcmipp_pins_a>; + pinctrl-1 = <&dcmipp_sleep_pins_a>; + status = "okay"; + + port { + dcmipp_0: endpoint { + remote-endpoint = <&mipid02_2>; + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + }; + }; +}; + +ðernet1 { + status = "okay"; + pinctrl-0 = <ð1_rmii_pins_a>; + pinctrl-1 = <ð1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + phy-handle = <&phy0_eth1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0_eth1: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reg = <0>; + reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; @@ -201,6 +255,76 @@ /* spare dmas for other usage */ /delete-property/dmas; /delete-property/dma-names; + + stmipi: csi2rx@14 { + compatible = "st,st-mipid02"; + reg = <0x14>; + clocks = <&clk_mco1>; + clock-names = "xclk"; + VDDE-supply = <&scmi_v1v8_periph>; + VDDIN-supply = <&scmi_v1v8_periph>; + reset-gpios = <&mcp23017 2 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + + mipid02_0: endpoint { + data-lanes = <1 2>; + lane-polarities = <0 0 0>; + remote-endpoint = <&gc2145_ep>; + }; + }; + port@2 { + reg = <2>; + + mipid02_2: endpoint { + bus-width = <8>; + hsync-active = <0>; + vsync-active = <0>; + pclk-sample = <0>; + remote-endpoint = <&dcmipp_0>; + }; + }; + }; + }; + + gc2145: camera@3c { + compatible = "galaxycore,gc2145"; + reg = <0x3c>; + clocks = <&clk_ext_camera>; + iovdd-supply = <&scmi_v3v3_sw>; + avdd-supply = <&scmi_v3v3_sw>; + dvdd-supply = <&scmi_v3v3_sw>; + powerdown-gpios = <&mcp23017 3 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + reset-gpios = <&mcp23017 4 (GPIO_ACTIVE_LOW | GPIO_PUSH_PULL)>; + status = "okay"; + + port { + gc2145_ep: endpoint { + remote-endpoint = <&mipid02_0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <120000000 192000000 240000000>; + }; + }; + }; + + goodix: goodix-ts@5d { + compatible = "goodix,gt911"; + reg = <0x5d>; + pinctrl-names = "default"; + pinctrl-0 = <&goodix_pins_a>; + interrupt-parent = <&gpiof>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + AVDD28-supply = <&scmi_v3v3_sw>; + VDDIO-supply = <&scmi_v3v3_sw>; + touchscreen-size-x = <480>; + touchscreen-size-y = <272>; + status = "okay" ; + }; }; &iwdg2 { @@ -273,6 +397,7 @@ /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 7 of the expansion connector (CN8.7) using TIM3_CH4 func */ pinctrl-0 = <&pwm3_pins_a>; pinctrl-1 = <&pwm3_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -288,6 +413,7 @@ /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 31 of the expansion connector (CN8.31) using TIM4_CH2 func */ pinctrl-0 = <&pwm4_pins_a>; pinctrl-1 = <&pwm4_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -303,6 +429,7 @@ /delete-property/dma-names; status = "disabled"; pwm { + /* PWM output on pin 32 of the expansion connector (CN8.32) using TIM8_CH3 func */ pinctrl-0 = <&pwm8_pins_a>; pinctrl-1 = <&pwm8_sleep_pins_a>; pinctrl-names = "default", "sleep"; @@ -316,6 +443,7 @@ &timers14 { status = "disabled"; pwm { + /* PWM output on pin 33 of the expansion connector (CN8.33) using TIM14_CH1 func */ pinctrl-0 = <&pwm14_pins_a>; pinctrl-1 = <&pwm14_sleep_pins_a>; pinctrl-names = "default", "sleep"; diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi new file mode 100644 index 000000000000..ddad6497775b --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2024 Marek Vasut <marex@denx.de> + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/mfd/st,stpmic1.h> +#include <dt-bindings/regulator/st,stm32mp13-regulator.h> +#include "stm32mp13-pinctrl.dtsi" + +/ { + model = "DH electronics STM32MP13xx DHCOR SoM"; + compatible = "dh,stm32mp131a-dhcor-som", + "st,stm32mp131"; + + aliases { + mmc0 = &sdmmc2; + mmc1 = &sdmmc1; + serial0 = &uart4; + serial1 = &uart7; + rtc0 = &rv3032; + spi0 = &qspi; + }; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + optee@dd000000 { + reg = <0xdd000000 0x3000000>; + no-map; + }; + }; + + sdio_pwrseq: sdio-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpiof 12 GPIO_ACTIVE_LOW>; + }; + + vin: vin { + compatible = "regulator-fixed"; + regulator-name = "vin"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&i2c3 { + i2c-scl-rising-time-ns = <96>; + i2c-scl-falling-time-ns = <3>; + clock-frequency = <400000>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioi 3 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + status = "okay"; + + regulators { + compatible = "st,stpmic1-regulators"; + + ldo1-supply = <&vin>; + ldo2-supply = <&vin>; + ldo3-supply = <&vin>; + ldo4-supply = <&vin>; + ldo5-supply = <&vin>; + ldo6-supply = <&vin>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcpu: buck1 { /* VDD_CPU_1V2 */ + regulator-name = "vddcpu"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { /* VDD_DDR_1V35 */ + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { /* VDD_3V3_1V8 */ + regulator-name = "vdd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vddcore: buck4 { /* VDD_CORE_1V2 */ + regulator-name = "vddcore"; + regulator-min-microvolt = <1250000>; + regulator-max-microvolt = <1250000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_adc: ldo1 { /* VDD_ADC_1V8 */ + regulator-name = "vdd_adc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO1 0>; + }; + + vdd_ldo2: ldo2 { /* LDO2_OUT_1V8 */ + regulator-name = "vdd_ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO2 0>; + }; + + vdd_ldo3: ldo3 { /* LDO3_OUT */ + regulator-name = "vdd_ldo3"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + interrupts = <IT_CURLIM_LDO3 0>; + }; + + vdd_usb: ldo4 { /* VDD_USB_3V3 */ + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO4 0>; + }; + + vdd_sd: ldo5 { /* VDD_SD_3V3_1V8 */ + regulator-name = "vdd_sd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO5 0>; + }; + + vdd_sd2: ldo6 { /* VDD_SD2_3V3_1V8 */ + regulator-name = "vdd_sd2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + interrupts = <IT_CURLIM_LDO6 0>; + }; + + vref_ddr: vref_ddr { /* VREF_DDR_0V675 */ + regulator-name = "vref_ddr"; + regulator-always-on; + }; + + bst_out: boost { /* BST_OUT_5V2 */ + regulator-name = "bst_out"; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = <IT_OCP_OTG 0>; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = <IT_OCP_SWOUT 0>; + regulator-active-discharge = <1>; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = <IT_PONKEY_F 0>, <IT_PONKEY_R 1>; + interrupt-names = "onkey-falling", "onkey-rising"; + status = "okay"; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; + + eeprom0: eeprom@50 { + compatible = "atmel,24c256"; /* ST M24256 */ + reg = <0x50>; + pagesize = <64>; + }; + + rv3032: rtc@51 { + compatible = "microcrystal,rv3032"; + reg = <0x51>; + interrupts-extended = <&gpioi 0 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&qspi { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-rx-bus-width = <4>; + spi-max-frequency = <108000000>; + #address-cells = <1>; + #size-cells = <1>; + }; +}; + +/* Console UART */ +&uart4 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart4_pins_b>; + pinctrl-1 = <&uart4_sleep_pins_b>; + pinctrl-2 = <&uart4_idle_pins_b>; + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; +}; + +/* Bluetooth */ +&uart7 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&uart7_pins_a>; + pinctrl-1 = <&uart7_sleep_pins_a>; + pinctrl-2 = <&uart7_idle_pins_a>; + uart-has-rtscts; + status = "okay"; + + bluetooth { + compatible = "infineon,cyw43439-bt", "brcm,bcm4329-bt"; + max-speed = <3000000>; + device-wakeup-gpios = <&gpiog 9 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&gpioi 2 GPIO_ACTIVE_HIGH>; + }; +}; + +/* SDIO WiFi */ +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_clk_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a &sdmmc1_clk_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + bus-width = <4>; + cap-power-off-card; + keep-power-in-suspend; + non-removable; + st,neg-edge; + vmmc-supply = <&vdd>; + mmc-pwrseq = <&sdio_pwrseq>; + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + brcmf: bcrmf@1 { /* muRata 1YN */ + reg = <1>; + compatible = "infineon,cyw43439-fmac", "brcm,bcm4329-fmac"; + interrupt-parent = <&gpioe>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "host-wake"; + }; +}; + +/* eMMC */ +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_a &sdmmc2_clk_pins_a>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_a>; + bus-width = <8>; + mmc-ddr-3_3v; + no-sd; + no-sdio; + non-removable; + st,neg-edge; + vmmc-supply = <&vdd>; + vqmmc-supply = <&vdd>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts index 306e1bc2a514..847b360f02fc 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -62,6 +62,11 @@ reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts index 956da5f26c1c..43280289759d 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -68,6 +68,11 @@ reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts index 8e4b0db198c2..6f27d794d270 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -67,6 +67,11 @@ reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts index 72b9cab2d990..6ae391bffee5 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -72,6 +72,11 @@ reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts index 527c33be66cc..36e6055b5665 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-osd32mp1-red.dts @@ -147,11 +147,6 @@ status = "okay"; }; -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - &rtc { status = "okay"; }; @@ -211,11 +206,3 @@ &usbphyc { status = "okay"; }; - -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; diff --git a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi index cfaf8adde319..c87fd96cbd91 100644 --- a/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xc-lxa-tac.dtsi @@ -379,11 +379,6 @@ baseboard_eeprom: &sip_eeprom { }; }; -&pwr_regulators { - vdd-supply = <&vdd>; - vdd_3v3_usbfs-supply = <&vdd_usb>; -}; - &rtc { status = "okay"; }; @@ -590,14 +585,6 @@ baseboard_eeprom: &sip_eeprom { status = "okay"; }; -&usbphyc_port0 { - phy-supply = <&vdd_usb>; -}; - -&usbphyc_port1 { - phy-supply = <&vdd_usb>; -}; - &vrefbuf { regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; diff --git a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi index aeb71c41a734..2022a1fa31ca 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-osd32.dtsi @@ -214,3 +214,16 @@ &rng1 { status = "okay"; }; + +&pwr_regulators { + vdd-supply = <&vdd>; + vdd_3v3_usbfs-supply = <&vdd_usb>; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply = <&vdd_usb>; +}; diff --git a/arch/arm/boot/dts/ti/davinci/da850-evm.dts b/arch/arm/boot/dts/ti/davinci/da850-evm.dts index 6c5936278e75..1f5cd35f8b74 100644 --- a/arch/arm/boot/dts/ti/davinci/da850-evm.dts +++ b/arch/arm/boot/dts/ti/davinci/da850-evm.dts @@ -65,7 +65,7 @@ display-timings { native-mode = <&timing0>; - timing0: 480x272 { + timing0: timing-480x272 { clock-frequency = <9000000>; hactive = <480>; vactive = <272>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts index 56e5d954a490..4b070e634b28 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-guardian.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-guardian.dts @@ -74,7 +74,7 @@ pinctrl-1 = <&lcd_pins_sleep>; display-timings { - 320x240 { + timing-320x240 { hactive = <320>; vactive = <240>; hback-porch = <68>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts index f38f5bff2b96..17574d0d0525 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pdu001.dts @@ -67,7 +67,7 @@ }; display-timings { - 240x320p16 { + timing-240x320p16 { clock-frequency = <6500000>; hactive = <240>; vactive = <320>; diff --git a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts index d5a4a21889d1..e7d561a527fd 100644 --- a/arch/arm/boot/dts/ti/omap/am335x-pepper.dts +++ b/arch/arm/boot/dts/ti/omap/am335x-pepper.dts @@ -202,7 +202,7 @@ }; display-timings { native-mode = <&timing0>; - timing0: 480x272 { + timing0: timing-480x272 { clock-frequency = <18400000>; hactive = <480>; vactive = <272>; diff --git a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts index eb1ec85aba28..e6a18954e449 100644 --- a/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts +++ b/arch/arm/boot/dts/ti/omap/am5729-beagleboneai.dts @@ -196,7 +196,6 @@ extcon_usb1: extcon_usb1 { compatible = "linux,extcon-usb-gpio"; - ti,enable-id-detection; id-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/vt8500/vt8500-bv07.dts b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts index e9f55bd30bd4..38a2da5e2c5d 100644 --- a/arch/arm/boot/dts/vt8500/vt8500-bv07.dts +++ b/arch/arm/boot/dts/vt8500/vt8500-bv07.dts @@ -16,7 +16,7 @@ bits-per-pixel = <16>; display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing-800x480 { clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/vt8500/vt8500.dtsi b/arch/arm/boot/dts/vt8500/vt8500.dtsi index b7e09eff5bb2..f23cb5ee11ae 100644 --- a/arch/arm/boot/dts/vt8500/vt8500.dtsi +++ b/arch/arm/boot/dts/vt8500/vt8500.dtsi @@ -115,7 +115,7 @@ interrupts = <43>; }; - uhci@d8007b00 { + usb@d8007b00 { compatible = "platform-uhci"; reg = <0xd8007b00 0x200>; interrupts = <43>; diff --git a/arch/arm/boot/dts/vt8500/wm8505-ref.dts b/arch/arm/boot/dts/vt8500/wm8505-ref.dts index 2d77c087676e..8ce9e2ef0a81 100644 --- a/arch/arm/boot/dts/vt8500/wm8505-ref.dts +++ b/arch/arm/boot/dts/vt8500/wm8505-ref.dts @@ -16,7 +16,7 @@ bits-per-pixel = <32>; display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing-800x480 { clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/vt8500/wm8505.dtsi b/arch/arm/boot/dts/vt8500/wm8505.dtsi index 168cd12b07bc..d9e1280372c5 100644 --- a/arch/arm/boot/dts/vt8500/wm8505.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8505.dtsi @@ -213,7 +213,7 @@ interrupts = <1>; }; - uhci@d8007300 { + usb@d8007300 { compatible = "platform-uhci"; reg = <0xd8007300 0x200>; interrupts = <0>; diff --git a/arch/arm/boot/dts/vt8500/wm8650-mid.dts b/arch/arm/boot/dts/vt8500/wm8650-mid.dts index f6a42149a0a0..7977b6c1e8eb 100644 --- a/arch/arm/boot/dts/vt8500/wm8650-mid.dts +++ b/arch/arm/boot/dts/vt8500/wm8650-mid.dts @@ -17,7 +17,7 @@ display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing-800x480 { clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/vt8500/wm8650.dtsi b/arch/arm/boot/dts/vt8500/wm8650.dtsi index bc057b6f7d16..35d12d77efc0 100644 --- a/arch/arm/boot/dts/vt8500/wm8650.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8650.dtsi @@ -185,7 +185,7 @@ interrupts = <43>; }; - uhci@d8007b00 { + usb@d8007b00 { compatible = "platform-uhci"; reg = <0xd8007b00 0x200>; interrupts = <43>; diff --git a/arch/arm/boot/dts/vt8500/wm8750.dtsi b/arch/arm/boot/dts/vt8500/wm8750.dtsi index 33aeb37491f4..b292f85d4e69 100644 --- a/arch/arm/boot/dts/vt8500/wm8750.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8750.dtsi @@ -257,13 +257,13 @@ interrupts = <26>; }; - uhci@d8007b00 { + usb@d8007b00 { compatible = "platform-uhci"; reg = <0xd8007b00 0x200>; interrupts = <26>; }; - uhci@d8008d00 { + usb@d8008d00 { compatible = "platform-uhci"; reg = <0xd8008d00 0x200>; interrupts = <26>; diff --git a/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts index c7a6fe0ce48f..5d409323b10c 100644 --- a/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts +++ b/arch/arm/boot/dts/vt8500/wm8850-w70v2.dts @@ -28,7 +28,7 @@ bits-per-pixel = <16>; display-timings { native-mode = <&timing0>; - timing0: 800x480 { + timing0: timing-800x480 { clock-frequency = <0>; /* unused but required */ hactive = <800>; vactive = <480>; diff --git a/arch/arm/boot/dts/vt8500/wm8850.dtsi b/arch/arm/boot/dts/vt8500/wm8850.dtsi index 65c9271050e6..c61717ebb4f1 100644 --- a/arch/arm/boot/dts/vt8500/wm8850.dtsi +++ b/arch/arm/boot/dts/vt8500/wm8850.dtsi @@ -244,13 +244,13 @@ interrupts = <26>; }; - uhci@d8007b00 { + usb@d8007b00 { compatible = "platform-uhci"; reg = <0xd8007b00 0x200>; interrupts = <26>; }; - uhci@d8008d00 { + usb@d8008d00 { compatible = "platform-uhci"; reg = <0xd8008d00 0x200>; interrupts = <26>; diff --git a/arch/arm/boot/install.sh b/arch/arm/boot/install.sh index 9ec11fac7d8d..34e2c6e31fd1 100755 --- a/arch/arm/boot/install.sh +++ b/arch/arm/boot/install.sh @@ -17,6 +17,8 @@ # $3 - kernel map file # $4 - default install path (blank if root directory) +set -e + if [ "$(basename $2)" = "zImage" ]; then # Compressed install echo "Installing compressed kernel" diff --git a/arch/arm/common/locomo.c b/arch/arm/common/locomo.c index 6d0c9f7268ba..06b0e5fd54a6 100644 --- a/arch/arm/common/locomo.c +++ b/arch/arm/common/locomo.c @@ -816,10 +816,10 @@ EXPORT_SYMBOL(locomo_frontlight_set); * We model this as a regular bus type, and hang devices directly * off this. */ -static int locomo_match(struct device *_dev, struct device_driver *_drv) +static int locomo_match(struct device *_dev, const struct device_driver *_drv) { struct locomo_dev *dev = LOCOMO_DEV(_dev); - struct locomo_driver *drv = LOCOMO_DRV(_drv); + const struct locomo_driver *drv = LOCOMO_DRV(_drv); return dev->devid == drv->devid; } diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c index 1fbd7363cf11..550978dc3c50 100644 --- a/arch/arm/common/sa1111.c +++ b/arch/arm/common/sa1111.c @@ -1339,10 +1339,10 @@ EXPORT_SYMBOL_GPL(sa1111_get_irq); * We model this as a regular bus type, and hang devices directly * off this. */ -static int sa1111_match(struct device *_dev, struct device_driver *_drv) +static int sa1111_match(struct device *_dev, const struct device_driver *_drv) { struct sa1111_dev *dev = to_sa1111_device(_dev); - struct sa1111_driver *drv = SA1111_DRV(_drv); + const struct sa1111_driver *drv = SA1111_DRV(_drv); return !!(dev->devid & drv->devid); } diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 1d53aec4c836..6eabe2313c9a 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -143,6 +143,7 @@ CONFIG_VIDEO_OV2640=m CONFIG_VIDEO_OV7740=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y +CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_FB_ATMEL=y diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index cf2480dce285..333ef55476a3 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -133,6 +133,7 @@ CONFIG_SMSC911X=y # CONFIG_NET_VENDOR_STMICRO is not set CONFIG_MICREL_PHY=y CONFIG_AT803X_PHY=y +CONFIG_DP83867_PHY=y CONFIG_CAN_FLEXCAN=y CONFIG_USB_PEGASUS=m CONFIG_USB_RTL8150=m @@ -180,6 +181,7 @@ CONFIG_TOUCHSCREEN_SX8654=y CONFIG_TOUCHSCREEN_COLIBRI_VF50=y CONFIG_INPUT_MISC=y CONFIG_INPUT_MMA8450=y +CONFIG_INPUT_GPIO_BEEPER=m CONFIG_SERIO_SERPORT=m # CONFIG_LEGACY_PTYS is not set CONFIG_SERIAL_IMX=y @@ -211,6 +213,7 @@ CONFIG_GPIO_SIOX=m CONFIG_GPIO_VF610=y CONFIG_GPIO_MAX732X=y CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PCF857X=y CONFIG_GPIO_BD71815=y CONFIG_GPIO_STMPE=y @@ -226,6 +229,7 @@ CONFIG_RN5T618_POWER=m CONFIG_SENSORS_MC13783_ADC=y CONFIG_SENSORS_GPIO_FAN=y CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SENSORS_LM75=m CONFIG_SENSORS_PWM_FAN=y CONFIG_SENSORS_SY7636A=y CONFIG_THERMAL_STATISTICS=y @@ -282,6 +286,9 @@ CONFIG_DRM_PANEL_LVDS=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y +CONFIG_DRM_DISPLAY_CONNECTOR=y +CONFIG_DRM_LVDS_CODEC=m +CONFIG_DRM_SII902X=y CONFIG_DRM_TI_TFP410=y CONFIG_DRM_DW_HDMI_AHB_AUDIO=m CONFIG_DRM_DW_HDMI_CEC=y @@ -311,7 +318,6 @@ CONFIG_SND_IMX_SOC=y CONFIG_SND_SOC_EUKREA_TLV320=y CONFIG_SND_SOC_IMX_ES8328=y CONFIG_SND_SOC_IMX_SGTL5000=y -CONFIG_SND_SOC_IMX_SPDIF=y CONFIG_SND_SOC_FSL_ASOC_CARD=y CONFIG_SND_SOC_AC97_CODEC=y CONFIG_SND_SOC_CS42XX8_I2C=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 86bf057ac366..62734530a3d6 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -469,6 +469,7 @@ CONFIG_SPI_XILINX=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_AS3722=y +CONFIG_PINCTRL_MCP23S08=m CONFIG_PINCTRL_MICROCHIP_SGPIO=y CONFIG_PINCTRL_OCELOT=y CONFIG_PINCTRL_PALMAS=y diff --git a/arch/arm/configs/vexpress_defconfig b/arch/arm/configs/vexpress_defconfig index 96ad442089bd..cdb6065e04fd 100644 --- a/arch/arm/configs/vexpress_defconfig +++ b/arch/arm/configs/vexpress_defconfig @@ -14,7 +14,6 @@ CONFIG_CPUSETS=y CONFIG_BLK_DEV_INITRD=y CONFIG_PROFILING=y CONFIG_ARCH_VEXPRESS=y -CONFIG_ARCH_VEXPRESS_DCSCB=y CONFIG_ARCH_VEXPRESS_TC2_PM=y CONFIG_SMP=y CONFIG_HAVE_ARM_ARCH_TIMER=y diff --git a/arch/arm/crypto/aes-neonbs-glue.c b/arch/arm/crypto/aes-neonbs-glue.c index f00f042ef357..201eb35dde37 100644 --- a/arch/arm/crypto/aes-neonbs-glue.c +++ b/arch/arm/crypto/aes-neonbs-glue.c @@ -17,6 +17,7 @@ #include <linux/module.h> MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); +MODULE_DESCRIPTION("Bit sliced AES using NEON instructions"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS_CRYPTO("ecb(aes)"); diff --git a/arch/arm/crypto/crc32-ce-core.S b/arch/arm/crypto/crc32-ce-core.S index 3f13a76b9066..88f9edf94e95 100644 --- a/arch/arm/crypto/crc32-ce-core.S +++ b/arch/arm/crypto/crc32-ce-core.S @@ -48,6 +48,7 @@ */ #include <linux/linkage.h> +#include <linux/cfi_types.h> #include <asm/assembler.h> .text @@ -123,11 +124,12 @@ * uint crc32_pmull_le(unsigned char const *buffer, * size_t len, uint crc32) */ -ENTRY(crc32_pmull_le) +SYM_FUNC_START(crc32_pmull_le) adr r3, .Lcrc32_constants b 0f +SYM_FUNC_END(crc32_pmull_le) -ENTRY(crc32c_pmull_le) +SYM_FUNC_START(crc32c_pmull_le) adr r3, .Lcrc32c_constants 0: bic LEN, LEN, #15 @@ -236,8 +238,7 @@ fold_64: vmov r0, s5 bx lr -ENDPROC(crc32_pmull_le) -ENDPROC(crc32c_pmull_le) +SYM_FUNC_END(crc32c_pmull_le) .macro __crc32, c subs ip, r2, #8 @@ -296,11 +297,11 @@ ARM_BE8(rev16 r3, r3 ) .endm .align 5 -ENTRY(crc32_armv8_le) +SYM_TYPED_FUNC_START(crc32_armv8_le) __crc32 -ENDPROC(crc32_armv8_le) +SYM_FUNC_END(crc32_armv8_le) .align 5 -ENTRY(crc32c_armv8_le) +SYM_TYPED_FUNC_START(crc32c_armv8_le) __crc32 c -ENDPROC(crc32c_armv8_le) +SYM_FUNC_END(crc32c_armv8_le) diff --git a/arch/arm/crypto/crc32-ce-glue.c b/arch/arm/crypto/crc32-ce-glue.c index 2208445808d7..4ff18044af07 100644 --- a/arch/arm/crypto/crc32-ce-glue.c +++ b/arch/arm/crypto/crc32-ce-glue.c @@ -241,6 +241,7 @@ module_init(crc32_pmull_mod_init); module_exit(crc32_pmull_mod_exit); MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); +MODULE_DESCRIPTION("Accelerated CRC32(C) using ARM CRC, NEON and Crypto Extensions"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS_CRYPTO("crc32"); MODULE_ALIAS_CRYPTO("crc32c"); diff --git a/arch/arm/crypto/crct10dif-ce-glue.c b/arch/arm/crypto/crct10dif-ce-glue.c index e9191a8c87b9..79f3b204d8c0 100644 --- a/arch/arm/crypto/crct10dif-ce-glue.c +++ b/arch/arm/crypto/crct10dif-ce-glue.c @@ -84,5 +84,6 @@ module_init(crc_t10dif_mod_init); module_exit(crc_t10dif_mod_exit); MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>"); +MODULE_DESCRIPTION("Accelerated CRC-T10DIF using ARM NEON and Crypto Extensions"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS_CRYPTO("crct10dif"); diff --git a/arch/arm/crypto/curve25519-glue.c b/arch/arm/crypto/curve25519-glue.c index 9bdafd57888c..e7b87e09dd99 100644 --- a/arch/arm/crypto/curve25519-glue.c +++ b/arch/arm/crypto/curve25519-glue.c @@ -133,4 +133,5 @@ module_exit(arm_curve25519_exit); MODULE_ALIAS_CRYPTO("curve25519"); MODULE_ALIAS_CRYPTO("curve25519-neon"); +MODULE_DESCRIPTION("Public key crypto: Curve25519 (NEON-accelerated)"); MODULE_LICENSE("GPL v2"); diff --git a/arch/arm/crypto/poly1305-glue.c b/arch/arm/crypto/poly1305-glue.c index c31bd8f7c092..8482e302c45a 100644 --- a/arch/arm/crypto/poly1305-glue.c +++ b/arch/arm/crypto/poly1305-glue.c @@ -267,6 +267,7 @@ static void __exit arm_poly1305_mod_exit(void) module_init(arm_poly1305_mod_init); module_exit(arm_poly1305_mod_exit); +MODULE_DESCRIPTION("Accelerated Poly1305 transform for ARM"); MODULE_LICENSE("GPL v2"); MODULE_ALIAS_CRYPTO("poly1305"); MODULE_ALIAS_CRYPTO("poly1305-arm"); diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h index 1075534b0a2e..8ed8b9a24efe 100644 --- a/arch/arm/include/asm/cacheflush.h +++ b/arch/arm/include/asm/cacheflush.h @@ -283,7 +283,7 @@ void flush_cache_pages(struct vm_area_struct *vma, unsigned long user_addr, * flush_dcache_page is used when the kernel has written to the page * cache page at virtual address page->virtual. * - * If this page isn't mapped (ie, page_mapping == NULL), or it might + * If this page isn't mapped (ie, folio_mapping == NULL), or it might * have userspace mappings, then we _must_ always clean + invalidate * the dcache entries associated with the kernel mapping. * diff --git a/arch/arm/include/asm/cmpxchg.h b/arch/arm/include/asm/cmpxchg.h index 44667bdb4707..9beb64d30586 100644 --- a/arch/arm/include/asm/cmpxchg.h +++ b/arch/arm/include/asm/cmpxchg.h @@ -5,6 +5,7 @@ #include <linux/irqflags.h> #include <linux/prefetch.h> #include <asm/barrier.h> +#include <linux/cmpxchg-emu.h> #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110) /* @@ -162,7 +163,11 @@ static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old, prefetchw((const void *)ptr); switch (size) { -#ifndef CONFIG_CPU_V6 /* min ARCH >= ARMv6K */ +#ifdef CONFIG_CPU_V6 /* ARCH == ARMv6 */ + case 1: + oldval = cmpxchg_emu_u8((volatile u8 *)ptr, old, new); + break; +#else /* min ARCH > ARMv6 */ case 1: do { asm volatile("@ __cmpxchg1\n" diff --git a/arch/arm/include/asm/hardware/locomo.h b/arch/arm/include/asm/hardware/locomo.h index 9fd9ad5d9202..3190e1e5067a 100644 --- a/arch/arm/include/asm/hardware/locomo.h +++ b/arch/arm/include/asm/hardware/locomo.h @@ -189,7 +189,7 @@ struct locomo_driver { void (*remove)(struct locomo_dev *); }; -#define LOCOMO_DRV(_d) container_of((_d), struct locomo_driver, drv) +#define LOCOMO_DRV(_d) container_of_const((_d), struct locomo_driver, drv) #define LOCOMO_DRIVER_NAME(_ldev) ((_ldev)->dev.driver->name) diff --git a/arch/arm/include/asm/hardware/sa1111.h b/arch/arm/include/asm/hardware/sa1111.h index d8c6f8a99dfa..a815f39b4243 100644 --- a/arch/arm/include/asm/hardware/sa1111.h +++ b/arch/arm/include/asm/hardware/sa1111.h @@ -404,7 +404,7 @@ struct sa1111_driver { void (*remove)(struct sa1111_dev *); }; -#define SA1111_DRV(_d) container_of((_d), struct sa1111_driver, drv) +#define SA1111_DRV(_d) container_of_const((_d), struct sa1111_driver, drv) #define SA1111_DRIVER_NAME(_sadev) ((_sadev)->dev.driver->name) diff --git a/arch/arm/include/asm/hugetlb-3level.h b/arch/arm/include/asm/hugetlb-3level.h index a30be5505793..87d48e2d90ad 100644 --- a/arch/arm/include/asm/hugetlb-3level.h +++ b/arch/arm/include/asm/hugetlb-3level.h @@ -13,12 +13,12 @@ /* * If our huge pte is non-zero then mark the valid bit. - * This allows pte_present(huge_ptep_get(ptep)) to return true for non-zero + * This allows pte_present(huge_ptep_get(mm,addr,ptep)) to return true for non-zero * ptes. * (The valid bit is automatically cleared by set_pte_at for PROT_NONE ptes). */ #define __HAVE_ARCH_HUGE_PTEP_GET -static inline pte_t huge_ptep_get(pte_t *ptep) +static inline pte_t huge_ptep_get(struct mm_struct *mm, unsigned long addr, pte_t *ptep) { pte_t retval = *ptep; if (pte_val(retval)) diff --git a/arch/arm/include/asm/stacktrace.h b/arch/arm/include/asm/stacktrace.h index 360f0d2406bf..f80a85b091d6 100644 --- a/arch/arm/include/asm/stacktrace.h +++ b/arch/arm/include/asm/stacktrace.h @@ -26,6 +26,13 @@ struct stackframe { #endif }; +static inline bool on_thread_stack(void) +{ + unsigned long delta = current_stack_pointer ^ (unsigned long)current->stack; + + return delta < THREAD_SIZE; +} + static __always_inline void arm_get_current_stackframe(struct pt_regs *regs, struct stackframe *frame) { diff --git a/arch/arm/include/asm/unistd.h b/arch/arm/include/asm/unistd.h index 3676e82cf95c..9fb00973c608 100644 --- a/arch/arm/include/asm/unistd.h +++ b/arch/arm/include/asm/unistd.h @@ -37,7 +37,6 @@ #define __ARCH_WANT_SYS_FORK #define __ARCH_WANT_SYS_VFORK #define __ARCH_WANT_SYS_CLONE -#define __ARCH_WANT_SYS_CLONE3 /* * Unimplemented (or alternatively implemented) syscalls diff --git a/arch/arm/include/asm/vmlinux.lds.h b/arch/arm/include/asm/vmlinux.lds.h index 4c8632d5c432..d60f6e83a9f7 100644 --- a/arch/arm/include/asm/vmlinux.lds.h +++ b/arch/arm/include/asm/vmlinux.lds.h @@ -42,7 +42,7 @@ #define PROC_INFO \ . = ALIGN(4); \ __proc_info_begin = .; \ - *(.proc.info.init) \ + KEEP(*(.proc.info.init)) \ __proc_info_end = .; #define IDMAP_TEXT \ diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile index 89a77e3f51d2..aaae31b8c4a5 100644 --- a/arch/arm/kernel/Makefile +++ b/arch/arm/kernel/Makefile @@ -78,8 +78,6 @@ obj-$(CONFIG_CPU_XSC3) += xscale-cp0.o obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o obj-$(CONFIG_IWMMXT) += iwmmxt.o obj-$(CONFIG_PERF_EVENTS) += perf_regs.o perf_callchain.o -obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_xscale.o perf_event_v6.o \ - perf_event_v7.o AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o obj-$(CONFIG_VDSO) += vdso.o diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S index 6150a716828c..1dfae1af8e31 100644 --- a/arch/arm/kernel/entry-armv.S +++ b/arch/arm/kernel/entry-armv.S @@ -29,6 +29,12 @@ #include "entry-header.S" #include <asm/probes.h> +#ifdef CONFIG_HAVE_LD_DEAD_CODE_DATA_ELIMINATION +#define RELOC_TEXT_NONE .reloc .text, R_ARM_NONE, . +#else +#define RELOC_TEXT_NONE +#endif + /* * Interrupt handling. */ @@ -1065,6 +1071,7 @@ vector_addrexcptn: .globl vector_fiq .section .vectors, "ax", %progbits + RELOC_TEXT_NONE W(b) vector_rst W(b) vector_und ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_swi ) @@ -1078,6 +1085,7 @@ THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_swi ) #ifdef CONFIG_HARDEN_BRANCH_HISTORY .section .vectors.bhb.loop8, "ax", %progbits + RELOC_TEXT_NONE W(b) vector_rst W(b) vector_bhb_loop8_und ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_loop8_swi ) @@ -1090,6 +1098,7 @@ THUMB( .reloc ., R_ARM_THM_PC12, .L__vector_bhb_loop8_swi ) W(b) vector_bhb_loop8_fiq .section .vectors.bhb.bpiall, "ax", %progbits + RELOC_TEXT_NONE W(b) vector_rst W(b) vector_bhb_bpiall_und ARM( .reloc ., R_ARM_LDR_PC_G0, .L__vector_bhb_bpiall_swi ) diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 5c31e9de7a60..f379c852dcb7 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -119,6 +119,9 @@ no_work_pending: ct_user_enter save = 0 +#ifdef CONFIG_GCC_PLUGIN_STACKLEAK + bl stackleak_erase_on_task_stack +#endif restore_user_regs fast = 0, offset = 0 ENDPROC(ret_to_user_from_irq) ENDPROC(ret_to_user) diff --git a/arch/arm/kernel/module.c b/arch/arm/kernel/module.c index 677f218f7e84..da488d92e7a0 100644 --- a/arch/arm/kernel/module.c +++ b/arch/arm/kernel/module.c @@ -395,11 +395,6 @@ apply_relocate(Elf32_Shdr *sechdrs, const char *strtab, unsigned int symindex, return 0; } -struct mod_unwind_map { - const Elf_Shdr *unw_sec; - const Elf_Shdr *txt_sec; -}; - static const Elf_Shdr *find_mod_section(const Elf32_Ehdr *hdr, const Elf_Shdr *sechdrs, const char *name) { diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c deleted file mode 100644 index d9fd53841591..000000000000 --- a/arch/arm/kernel/perf_event_v6.c +++ /dev/null @@ -1,448 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARMv6 Performance counter handling code. - * - * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles - * - * ARMv6 has 2 configurable performance counters and a single cycle counter. - * They all share a single reset bit but can be written to zero so we can use - * that for a reset. - * - * The counters can't be individually enabled or disabled so when we remove - * one event and replace it with another we could get spurious counts from the - * wrong event. However, we can take advantage of the fact that the - * performance counters can export events to the event bus, and the event bus - * itself can be monitored. This requires that we *don't* export the events to - * the event bus. The procedure for disabling a configurable counter is: - * - change the counter to count the ETMEXTOUT[0] signal (0x20). This - * effectively stops the counter from counting. - * - disable the counter's interrupt generation (each counter has it's - * own interrupt enable bit). - * Once stopped, the counter value can be written as 0 to reset. - * - * To enable a counter: - * - enable the counter's interrupt generation. - * - set the new event type. - * - * Note: the dedicated cycle counter only counts cycles and can't be - * enabled/disabled independently of the others. When we want to disable the - * cycle counter, we have to just disable the interrupt reporting and start - * ignoring that counter. When re-enabling, we have to reset the value and - * enable the interrupt. - */ - -#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) - -#include <asm/cputype.h> -#include <asm/irq_regs.h> - -#include <linux/of.h> -#include <linux/perf/arm_pmu.h> -#include <linux/platform_device.h> - -enum armv6_perf_types { - ARMV6_PERFCTR_ICACHE_MISS = 0x0, - ARMV6_PERFCTR_IBUF_STALL = 0x1, - ARMV6_PERFCTR_DDEP_STALL = 0x2, - ARMV6_PERFCTR_ITLB_MISS = 0x3, - ARMV6_PERFCTR_DTLB_MISS = 0x4, - ARMV6_PERFCTR_BR_EXEC = 0x5, - ARMV6_PERFCTR_BR_MISPREDICT = 0x6, - ARMV6_PERFCTR_INSTR_EXEC = 0x7, - ARMV6_PERFCTR_DCACHE_HIT = 0x9, - ARMV6_PERFCTR_DCACHE_ACCESS = 0xA, - ARMV6_PERFCTR_DCACHE_MISS = 0xB, - ARMV6_PERFCTR_DCACHE_WBACK = 0xC, - ARMV6_PERFCTR_SW_PC_CHANGE = 0xD, - ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF, - ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10, - ARMV6_PERFCTR_LSU_FULL_STALL = 0x11, - ARMV6_PERFCTR_WBUF_DRAINED = 0x12, - ARMV6_PERFCTR_CPU_CYCLES = 0xFF, - ARMV6_PERFCTR_NOP = 0x20, -}; - -enum armv6_counters { - ARMV6_CYCLE_COUNTER = 0, - ARMV6_COUNTER0, - ARMV6_COUNTER1, -}; - -/* - * The hardware events that we support. We do support cache operations but - * we have harvard caches and no way to combine instruction and data - * accesses/misses in hardware. - */ -static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT, - [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV6_PERFCTR_IBUF_STALL, - [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV6_PERFCTR_LSU_FULL_STALL, -}; - -static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - /* - * The performance counters don't differentiate between read and write - * accesses/misses so this isn't strictly correct, but it's the best we - * can do. Writes and reads get combined. - */ - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS, - - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS, - - /* - * The ARM performance counters can count micro DTLB misses, micro ITLB - * misses and main TLB misses. There isn't an event for TLB misses, so - * use the micro misses here and if users want the main TLB misses they - * can use a raw counter. - */ - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS, - - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS, -}; - -static inline unsigned long -armv6_pmcr_read(void) -{ - u32 val; - asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val)); - return val; -} - -static inline void -armv6_pmcr_write(unsigned long val) -{ - asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val)); -} - -#define ARMV6_PMCR_ENABLE (1 << 0) -#define ARMV6_PMCR_CTR01_RESET (1 << 1) -#define ARMV6_PMCR_CCOUNT_RESET (1 << 2) -#define ARMV6_PMCR_CCOUNT_DIV (1 << 3) -#define ARMV6_PMCR_COUNT0_IEN (1 << 4) -#define ARMV6_PMCR_COUNT1_IEN (1 << 5) -#define ARMV6_PMCR_CCOUNT_IEN (1 << 6) -#define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8) -#define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9) -#define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10) -#define ARMV6_PMCR_EVT_COUNT0_SHIFT 20 -#define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT) -#define ARMV6_PMCR_EVT_COUNT1_SHIFT 12 -#define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT) - -#define ARMV6_PMCR_OVERFLOWED_MASK \ - (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \ - ARMV6_PMCR_CCOUNT_OVERFLOW) - -static inline int -armv6_pmcr_has_overflowed(unsigned long pmcr) -{ - return pmcr & ARMV6_PMCR_OVERFLOWED_MASK; -} - -static inline int -armv6_pmcr_counter_has_overflowed(unsigned long pmcr, - enum armv6_counters counter) -{ - int ret = 0; - - if (ARMV6_CYCLE_COUNTER == counter) - ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW; - else if (ARMV6_COUNTER0 == counter) - ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW; - else if (ARMV6_COUNTER1 == counter) - ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW; - else - WARN_ONCE(1, "invalid counter number (%d)\n", counter); - - return ret; -} - -static inline u64 armv6pmu_read_counter(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - int counter = hwc->idx; - unsigned long value = 0; - - if (ARMV6_CYCLE_COUNTER == counter) - asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value)); - else if (ARMV6_COUNTER0 == counter) - asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value)); - else if (ARMV6_COUNTER1 == counter) - asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value)); - else - WARN_ONCE(1, "invalid counter number (%d)\n", counter); - - return value; -} - -static inline void armv6pmu_write_counter(struct perf_event *event, u64 value) -{ - struct hw_perf_event *hwc = &event->hw; - int counter = hwc->idx; - - if (ARMV6_CYCLE_COUNTER == counter) - asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value)); - else if (ARMV6_COUNTER0 == counter) - asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value)); - else if (ARMV6_COUNTER1 == counter) - asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value)); - else - WARN_ONCE(1, "invalid counter number (%d)\n", counter); -} - -static void armv6pmu_enable_event(struct perf_event *event) -{ - unsigned long val, mask, evt; - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - if (ARMV6_CYCLE_COUNTER == idx) { - mask = 0; - evt = ARMV6_PMCR_CCOUNT_IEN; - } else if (ARMV6_COUNTER0 == idx) { - mask = ARMV6_PMCR_EVT_COUNT0_MASK; - evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) | - ARMV6_PMCR_COUNT0_IEN; - } else if (ARMV6_COUNTER1 == idx) { - mask = ARMV6_PMCR_EVT_COUNT1_MASK; - evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) | - ARMV6_PMCR_COUNT1_IEN; - } else { - WARN_ONCE(1, "invalid counter number (%d)\n", idx); - return; - } - - /* - * Mask out the current event and set the counter to count the event - * that we're interested in. - */ - val = armv6_pmcr_read(); - val &= ~mask; - val |= evt; - armv6_pmcr_write(val); -} - -static irqreturn_t -armv6pmu_handle_irq(struct arm_pmu *cpu_pmu) -{ - unsigned long pmcr = armv6_pmcr_read(); - struct perf_sample_data data; - struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); - struct pt_regs *regs; - int idx; - - if (!armv6_pmcr_has_overflowed(pmcr)) - return IRQ_NONE; - - regs = get_irq_regs(); - - /* - * The interrupts are cleared by writing the overflow flags back to - * the control register. All of the other bits don't have any effect - * if they are rewritten, so write the whole value back. - */ - armv6_pmcr_write(pmcr); - - for (idx = 0; idx < cpu_pmu->num_events; ++idx) { - struct perf_event *event = cpuc->events[idx]; - struct hw_perf_event *hwc; - - /* Ignore if we don't have an event. */ - if (!event) - continue; - - /* - * We have a single interrupt for all counters. Check that - * each counter has overflowed before we process it. - */ - if (!armv6_pmcr_counter_has_overflowed(pmcr, idx)) - continue; - - hwc = &event->hw; - armpmu_event_update(event); - perf_sample_data_init(&data, 0, hwc->last_period); - if (!armpmu_event_set_period(event)) - continue; - - if (perf_event_overflow(event, &data, regs)) - cpu_pmu->disable(event); - } - - /* - * Handle the pending perf events. - * - * Note: this call *must* be run with interrupts disabled. For - * platforms that can have the PMU interrupts raised as an NMI, this - * will not work. - */ - irq_work_run(); - - return IRQ_HANDLED; -} - -static void armv6pmu_start(struct arm_pmu *cpu_pmu) -{ - unsigned long val; - - val = armv6_pmcr_read(); - val |= ARMV6_PMCR_ENABLE; - armv6_pmcr_write(val); -} - -static void armv6pmu_stop(struct arm_pmu *cpu_pmu) -{ - unsigned long val; - - val = armv6_pmcr_read(); - val &= ~ARMV6_PMCR_ENABLE; - armv6_pmcr_write(val); -} - -static int -armv6pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - /* Always place a cycle counter into the cycle counter. */ - if (ARMV6_PERFCTR_CPU_CYCLES == hwc->config_base) { - if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask)) - return -EAGAIN; - - return ARMV6_CYCLE_COUNTER; - } else { - /* - * For anything other than a cycle counter, try and use - * counter0 and counter1. - */ - if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) - return ARMV6_COUNTER1; - - if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) - return ARMV6_COUNTER0; - - /* The counters are all in use. */ - return -EAGAIN; - } -} - -static void armv6pmu_clear_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - clear_bit(event->hw.idx, cpuc->used_mask); -} - -static void armv6pmu_disable_event(struct perf_event *event) -{ - unsigned long val, mask, evt; - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - if (ARMV6_CYCLE_COUNTER == idx) { - mask = ARMV6_PMCR_CCOUNT_IEN; - evt = 0; - } else if (ARMV6_COUNTER0 == idx) { - mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK; - evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT; - } else if (ARMV6_COUNTER1 == idx) { - mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK; - evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT; - } else { - WARN_ONCE(1, "invalid counter number (%d)\n", idx); - return; - } - - /* - * Mask out the current event and set the counter to count the number - * of ETM bus signal assertion cycles. The external reporting should - * be disabled and so this should never increment. - */ - val = armv6_pmcr_read(); - val &= ~mask; - val |= evt; - armv6_pmcr_write(val); -} - -static int armv6_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &armv6_perf_map, - &armv6_perf_cache_map, 0xFF); -} - -static void armv6pmu_init(struct arm_pmu *cpu_pmu) -{ - cpu_pmu->handle_irq = armv6pmu_handle_irq; - cpu_pmu->enable = armv6pmu_enable_event; - cpu_pmu->disable = armv6pmu_disable_event; - cpu_pmu->read_counter = armv6pmu_read_counter; - cpu_pmu->write_counter = armv6pmu_write_counter; - cpu_pmu->get_event_idx = armv6pmu_get_event_idx; - cpu_pmu->clear_event_idx = armv6pmu_clear_event_idx; - cpu_pmu->start = armv6pmu_start; - cpu_pmu->stop = armv6pmu_stop; - cpu_pmu->map_event = armv6_map_event; - cpu_pmu->num_events = 3; -} - -static int armv6_1136_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv6pmu_init(cpu_pmu); - cpu_pmu->name = "armv6_1136"; - return 0; -} - -static int armv6_1156_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv6pmu_init(cpu_pmu); - cpu_pmu->name = "armv6_1156"; - return 0; -} - -static int armv6_1176_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv6pmu_init(cpu_pmu); - cpu_pmu->name = "armv6_1176"; - return 0; -} - -static const struct of_device_id armv6_pmu_of_device_ids[] = { - {.compatible = "arm,arm1176-pmu", .data = armv6_1176_pmu_init}, - {.compatible = "arm,arm1136-pmu", .data = armv6_1136_pmu_init}, - { /* sentinel value */ } -}; - -static const struct pmu_probe_info armv6_pmu_probe_table[] = { - ARM_PMU_PROBE(ARM_CPU_PART_ARM1136, armv6_1136_pmu_init), - ARM_PMU_PROBE(ARM_CPU_PART_ARM1156, armv6_1156_pmu_init), - ARM_PMU_PROBE(ARM_CPU_PART_ARM1176, armv6_1176_pmu_init), - { /* sentinel value */ } -}; - -static int armv6_pmu_device_probe(struct platform_device *pdev) -{ - return arm_pmu_device_probe(pdev, armv6_pmu_of_device_ids, - armv6_pmu_probe_table); -} - -static struct platform_driver armv6_pmu_driver = { - .driver = { - .name = "armv6-pmu", - .of_match_table = armv6_pmu_of_device_ids, - }, - .probe = armv6_pmu_device_probe, -}; - -builtin_platform_driver(armv6_pmu_driver); -#endif /* CONFIG_CPU_V6 || CONFIG_CPU_V6K */ diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c deleted file mode 100644 index a3322e2b3ea4..000000000000 --- a/arch/arm/kernel/perf_event_v7.c +++ /dev/null @@ -1,2005 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. - * - * ARMv7 support: Jean Pihet <jpihet@mvista.com> - * 2010 (c) MontaVista Software, LLC. - * - * Copied from ARMv6 code, with the low level code inspired - * by the ARMv7 Oprofile code. - * - * Cortex-A8 has up to 4 configurable performance counters and - * a single cycle counter. - * Cortex-A9 has up to 31 configurable performance counters and - * a single cycle counter. - * - * All counters can be enabled/disabled and IRQ masked separately. The cycle - * counter and all 4 performance counters together can be reset separately. - */ - -#ifdef CONFIG_CPU_V7 - -#include <asm/cp15.h> -#include <asm/cputype.h> -#include <asm/irq_regs.h> -#include <asm/vfp.h> -#include "../vfp/vfpinstr.h" - -#include <linux/of.h> -#include <linux/perf/arm_pmu.h> -#include <linux/platform_device.h> - -/* - * Common ARMv7 event types - * - * Note: An implementation may not be able to count all of these events - * but the encodings are considered to be `reserved' in the case that - * they are not available. - */ -#define ARMV7_PERFCTR_PMNC_SW_INCR 0x00 -#define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01 -#define ARMV7_PERFCTR_ITLB_REFILL 0x02 -#define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03 -#define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04 -#define ARMV7_PERFCTR_DTLB_REFILL 0x05 -#define ARMV7_PERFCTR_MEM_READ 0x06 -#define ARMV7_PERFCTR_MEM_WRITE 0x07 -#define ARMV7_PERFCTR_INSTR_EXECUTED 0x08 -#define ARMV7_PERFCTR_EXC_TAKEN 0x09 -#define ARMV7_PERFCTR_EXC_EXECUTED 0x0A -#define ARMV7_PERFCTR_CID_WRITE 0x0B - -/* - * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. - * It counts: - * - all (taken) branch instructions, - * - instructions that explicitly write the PC, - * - exception generating instructions. - */ -#define ARMV7_PERFCTR_PC_WRITE 0x0C -#define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D -#define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E -#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F -#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10 -#define ARMV7_PERFCTR_CLOCK_CYCLES 0x11 -#define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12 - -/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ -#define ARMV7_PERFCTR_MEM_ACCESS 0x13 -#define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14 -#define ARMV7_PERFCTR_L1_DCACHE_WB 0x15 -#define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16 -#define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17 -#define ARMV7_PERFCTR_L2_CACHE_WB 0x18 -#define ARMV7_PERFCTR_BUS_ACCESS 0x19 -#define ARMV7_PERFCTR_MEM_ERROR 0x1A -#define ARMV7_PERFCTR_INSTR_SPEC 0x1B -#define ARMV7_PERFCTR_TTBR_WRITE 0x1C -#define ARMV7_PERFCTR_BUS_CYCLES 0x1D - -#define ARMV7_PERFCTR_CPU_CYCLES 0xFF - -/* ARMv7 Cortex-A8 specific event types */ -#define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43 -#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44 -#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50 -#define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56 - -/* ARMv7 Cortex-A9 specific event types */ -#define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68 -#define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60 -#define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66 - -/* ARMv7 Cortex-A5 specific event types */ -#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2 -#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3 - -/* ARMv7 Cortex-A15 specific event types */ -#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 -#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 -#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42 -#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43 - -#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C -#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D - -#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50 -#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 -#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52 -#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53 - -#define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76 - -/* ARMv7 Cortex-A12 specific event types */ -#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 -#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 - -#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50 -#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 - -#define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76 - -#define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7 - -/* ARMv7 Krait specific event types */ -#define KRAIT_PMRESR0_GROUP0 0xcc -#define KRAIT_PMRESR1_GROUP0 0xd0 -#define KRAIT_PMRESR2_GROUP0 0xd4 -#define KRAIT_VPMRESR0_GROUP0 0xd8 - -#define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011 -#define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010 - -#define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222 -#define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210 - -/* ARMv7 Scorpion specific event types */ -#define SCORPION_LPM0_GROUP0 0x4c -#define SCORPION_LPM1_GROUP0 0x50 -#define SCORPION_LPM2_GROUP0 0x54 -#define SCORPION_L2LPM_GROUP0 0x58 -#define SCORPION_VLPM_GROUP0 0x5c - -#define SCORPION_ICACHE_ACCESS 0x10053 -#define SCORPION_ICACHE_MISS 0x10052 - -#define SCORPION_DTLB_ACCESS 0x12013 -#define SCORPION_DTLB_MISS 0x12012 - -#define SCORPION_ITLB_MISS 0x12021 - -/* - * Cortex-A8 HW events mapping - * - * The hardware events that we support. We do support cache operations but - * we have harvard caches and no way to combine instruction and data - * accesses/misses in hardware. - */ -static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, - [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE, -}; - -static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - /* - * The performance counters don't differentiate between read and write - * accesses/misses so this isn't strictly correct, but it's the best we - * can do. Writes and reads get combined. - */ - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - - [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, - - [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, - [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, - [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, - [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, - - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - - [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -/* - * Cortex-A9 HW events mapping - */ -static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME, - [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE, - [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH, -}; - -static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - /* - * The performance counters don't differentiate between read and write - * accesses/misses so this isn't strictly correct, but it's the best we - * can do. Writes and reads get combined. - */ - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, - - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - - [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -/* - * Cortex-A5 HW events mapping - */ -static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, - [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, - [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, - - [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, - /* - * The prefetch counters don't differentiate between the I side and the - * D side. - */ - [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, - [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, - - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - - [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -/* - * Cortex-A15 HW events mapping - */ -static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, - [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, -}; - -static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE, - - /* - * Not all performance counters differentiate between read and write - * accesses/misses so we're not always strictly correct, but it's the - * best we can do. Writes and reads get combined in these cases. - */ - [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, - - [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ, - [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ, - [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE, - [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE, - - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE, - - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - - [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -/* - * Cortex-A7 HW events mapping - */ -static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, - [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, -}; - -static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - /* - * The performance counters don't differentiate between read and write - * accesses/misses so this isn't strictly correct, but it's the best we - * can do. Writes and reads get combined. - */ - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - - [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, - - [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, - [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, - [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, - [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, - - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - - [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -/* - * Cortex-A12 HW events mapping - */ -static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, - [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, -}; - -static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - - /* - * Not all performance counters differentiate between read and write - * accesses/misses so we're not always strictly correct, but it's the - * best we can do. Writes and reads get combined in these cases. - */ - [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, - - [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ, - [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, - [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE, - [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, - - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, - [C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL, - - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, - - [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -/* - * Krait HW events mapping - */ -static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, -}; - -static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, -}; - -static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - /* - * The performance counters don't differentiate between read and write - * accesses/misses so this isn't strictly correct, but it's the best we - * can do. Writes and reads get combined. - */ - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - - [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, - - [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, - [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, - - [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, - [C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, - - [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -/* - * Scorpion HW events mapping - */ -static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, - [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, - [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, -}; - -static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - /* - * The performance counters don't differentiate between read and write - * accesses/misses so this isn't strictly correct, but it's the best we - * can do. Writes and reads get combined. - */ - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, - [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS, - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS, - /* - * Only ITLB misses and DTLB refills are supported. If users want the - * DTLB refills misses a raw counter must be used. - */ - [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, - [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, - [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, - [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, -}; - -PMU_FORMAT_ATTR(event, "config:0-7"); - -static struct attribute *armv7_pmu_format_attrs[] = { - &format_attr_event.attr, - NULL, -}; - -static struct attribute_group armv7_pmu_format_attr_group = { - .name = "format", - .attrs = armv7_pmu_format_attrs, -}; - -#define ARMV7_EVENT_ATTR_RESOLVE(m) #m -#define ARMV7_EVENT_ATTR(name, config) \ - PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, \ - "event=" ARMV7_EVENT_ATTR_RESOLVE(config)) - -ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR); -ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL); -ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL); -ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL); -ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS); -ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL); -ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ); -ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE); -ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED); -ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN); -ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED); -ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE); -ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE); -ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH); -ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN); -ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS); -ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED); -ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES); -ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED); - -static struct attribute *armv7_pmuv1_event_attrs[] = { - &armv7_event_attr_sw_incr.attr.attr, - &armv7_event_attr_l1i_cache_refill.attr.attr, - &armv7_event_attr_l1i_tlb_refill.attr.attr, - &armv7_event_attr_l1d_cache_refill.attr.attr, - &armv7_event_attr_l1d_cache.attr.attr, - &armv7_event_attr_l1d_tlb_refill.attr.attr, - &armv7_event_attr_ld_retired.attr.attr, - &armv7_event_attr_st_retired.attr.attr, - &armv7_event_attr_inst_retired.attr.attr, - &armv7_event_attr_exc_taken.attr.attr, - &armv7_event_attr_exc_return.attr.attr, - &armv7_event_attr_cid_write_retired.attr.attr, - &armv7_event_attr_pc_write_retired.attr.attr, - &armv7_event_attr_br_immed_retired.attr.attr, - &armv7_event_attr_br_return_retired.attr.attr, - &armv7_event_attr_unaligned_ldst_retired.attr.attr, - &armv7_event_attr_br_mis_pred.attr.attr, - &armv7_event_attr_cpu_cycles.attr.attr, - &armv7_event_attr_br_pred.attr.attr, - NULL, -}; - -static struct attribute_group armv7_pmuv1_events_attr_group = { - .name = "events", - .attrs = armv7_pmuv1_event_attrs, -}; - -ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS); -ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS); -ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB); -ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS); -ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL); -ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB); -ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS); -ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR); -ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC); -ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE); -ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES); - -static struct attribute *armv7_pmuv2_event_attrs[] = { - &armv7_event_attr_sw_incr.attr.attr, - &armv7_event_attr_l1i_cache_refill.attr.attr, - &armv7_event_attr_l1i_tlb_refill.attr.attr, - &armv7_event_attr_l1d_cache_refill.attr.attr, - &armv7_event_attr_l1d_cache.attr.attr, - &armv7_event_attr_l1d_tlb_refill.attr.attr, - &armv7_event_attr_ld_retired.attr.attr, - &armv7_event_attr_st_retired.attr.attr, - &armv7_event_attr_inst_retired.attr.attr, - &armv7_event_attr_exc_taken.attr.attr, - &armv7_event_attr_exc_return.attr.attr, - &armv7_event_attr_cid_write_retired.attr.attr, - &armv7_event_attr_pc_write_retired.attr.attr, - &armv7_event_attr_br_immed_retired.attr.attr, - &armv7_event_attr_br_return_retired.attr.attr, - &armv7_event_attr_unaligned_ldst_retired.attr.attr, - &armv7_event_attr_br_mis_pred.attr.attr, - &armv7_event_attr_cpu_cycles.attr.attr, - &armv7_event_attr_br_pred.attr.attr, - &armv7_event_attr_mem_access.attr.attr, - &armv7_event_attr_l1i_cache.attr.attr, - &armv7_event_attr_l1d_cache_wb.attr.attr, - &armv7_event_attr_l2d_cache.attr.attr, - &armv7_event_attr_l2d_cache_refill.attr.attr, - &armv7_event_attr_l2d_cache_wb.attr.attr, - &armv7_event_attr_bus_access.attr.attr, - &armv7_event_attr_memory_error.attr.attr, - &armv7_event_attr_inst_spec.attr.attr, - &armv7_event_attr_ttbr_write_retired.attr.attr, - &armv7_event_attr_bus_cycles.attr.attr, - NULL, -}; - -static struct attribute_group armv7_pmuv2_events_attr_group = { - .name = "events", - .attrs = armv7_pmuv2_event_attrs, -}; - -/* - * Perf Events' indices - */ -#define ARMV7_IDX_CYCLE_COUNTER 0 -#define ARMV7_IDX_COUNTER0 1 -#define ARMV7_IDX_COUNTER_LAST(cpu_pmu) \ - (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1) - -#define ARMV7_MAX_COUNTERS 32 -#define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1) - -/* - * ARMv7 low level PMNC access - */ - -/* - * Perf Event to low level counters mapping - */ -#define ARMV7_IDX_TO_COUNTER(x) \ - (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK) - -/* - * Per-CPU PMNC: config reg - */ -#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ -#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ -#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ -#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ -#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ -#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ -#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ -#define ARMV7_PMNC_N_MASK 0x1f -#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ - -/* - * FLAG: counters overflow flag status reg - */ -#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ -#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK - -/* - * PMXEVTYPER: Event selection reg - */ -#define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */ -#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ - -/* - * Event filters for PMUv2 - */ -#define ARMV7_EXCLUDE_PL1 BIT(31) -#define ARMV7_EXCLUDE_USER BIT(30) -#define ARMV7_INCLUDE_HYP BIT(27) - -/* - * Secure debug enable reg - */ -#define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */ - -static inline u32 armv7_pmnc_read(void) -{ - u32 val; - asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); - return val; -} - -static inline void armv7_pmnc_write(u32 val) -{ - val &= ARMV7_PMNC_MASK; - isb(); - asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); -} - -static inline int armv7_pmnc_has_overflowed(u32 pmnc) -{ - return pmnc & ARMV7_OVERFLOWED_MASK; -} - -static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx) -{ - return idx >= ARMV7_IDX_CYCLE_COUNTER && - idx <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); -} - -static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx) -{ - return pmnc & BIT(ARMV7_IDX_TO_COUNTER(idx)); -} - -static inline void armv7_pmnc_select_counter(int idx) -{ - u32 counter = ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter)); - isb(); -} - -static inline u64 armv7pmu_read_counter(struct perf_event *event) -{ - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - u32 value = 0; - - if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { - pr_err("CPU%u reading wrong counter %d\n", - smp_processor_id(), idx); - } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { - asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); - } else { - armv7_pmnc_select_counter(idx); - asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); - } - - return value; -} - -static inline void armv7pmu_write_counter(struct perf_event *event, u64 value) -{ - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { - pr_err("CPU%u writing wrong counter %d\n", - smp_processor_id(), idx); - } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { - asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" ((u32)value)); - } else { - armv7_pmnc_select_counter(idx); - asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" ((u32)value)); - } -} - -static inline void armv7_pmnc_write_evtsel(int idx, u32 val) -{ - armv7_pmnc_select_counter(idx); - val &= ARMV7_EVTYPE_MASK; - asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); -} - -static inline void armv7_pmnc_enable_counter(int idx) -{ - u32 counter = ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter))); -} - -static inline void armv7_pmnc_disable_counter(int idx) -{ - u32 counter = ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter))); -} - -static inline void armv7_pmnc_enable_intens(int idx) -{ - u32 counter = ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter))); -} - -static inline void armv7_pmnc_disable_intens(int idx) -{ - u32 counter = ARMV7_IDX_TO_COUNTER(idx); - asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter))); - isb(); - /* Clear the overflow flag in case an interrupt is pending. */ - asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(counter))); - isb(); -} - -static inline u32 armv7_pmnc_getreset_flags(void) -{ - u32 val; - - /* Read */ - asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); - - /* Write to clear flags */ - val &= ARMV7_FLAG_MASK; - asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); - - return val; -} - -#ifdef DEBUG -static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu) -{ - u32 val; - unsigned int cnt; - - pr_info("PMNC registers dump:\n"); - - asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); - pr_info("PMNC =0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); - pr_info("CNTENS=0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); - pr_info("INTENS=0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); - pr_info("FLAGS =0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); - pr_info("SELECT=0x%08x\n", val); - - asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); - pr_info("CCNT =0x%08x\n", val); - - for (cnt = ARMV7_IDX_COUNTER0; - cnt <= ARMV7_IDX_COUNTER_LAST(cpu_pmu); cnt++) { - armv7_pmnc_select_counter(cnt); - asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); - pr_info("CNT[%d] count =0x%08x\n", - ARMV7_IDX_TO_COUNTER(cnt), val); - asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); - pr_info("CNT[%d] evtsel=0x%08x\n", - ARMV7_IDX_TO_COUNTER(cnt), val); - } -} -#endif - -static void armv7pmu_enable_event(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); - int idx = hwc->idx; - - if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { - pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n", - smp_processor_id(), idx); - return; - } - - /* - * Enable counter and interrupt, and set the counter to count - * the event that we're interested in. - */ - - /* - * Disable counter - */ - armv7_pmnc_disable_counter(idx); - - /* - * Set event (if destined for PMNx counters) - * We only need to set the event for the cycle counter if we - * have the ability to perform event filtering. - */ - if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER) - armv7_pmnc_write_evtsel(idx, hwc->config_base); - - /* - * Enable interrupt for this counter - */ - armv7_pmnc_enable_intens(idx); - - /* - * Enable counter - */ - armv7_pmnc_enable_counter(idx); -} - -static void armv7pmu_disable_event(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); - int idx = hwc->idx; - - if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { - pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n", - smp_processor_id(), idx); - return; - } - - /* - * Disable counter and interrupt - */ - - /* - * Disable counter - */ - armv7_pmnc_disable_counter(idx); - - /* - * Disable interrupt for this counter - */ - armv7_pmnc_disable_intens(idx); -} - -static irqreturn_t armv7pmu_handle_irq(struct arm_pmu *cpu_pmu) -{ - u32 pmnc; - struct perf_sample_data data; - struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); - struct pt_regs *regs; - int idx; - - /* - * Get and reset the IRQ flags - */ - pmnc = armv7_pmnc_getreset_flags(); - - /* - * Did an overflow occur? - */ - if (!armv7_pmnc_has_overflowed(pmnc)) - return IRQ_NONE; - - /* - * Handle the counter(s) overflow(s) - */ - regs = get_irq_regs(); - - for (idx = 0; idx < cpu_pmu->num_events; ++idx) { - struct perf_event *event = cpuc->events[idx]; - struct hw_perf_event *hwc; - - /* Ignore if we don't have an event. */ - if (!event) - continue; - - /* - * We have a single interrupt for all counters. Check that - * each counter has overflowed before we process it. - */ - if (!armv7_pmnc_counter_has_overflowed(pmnc, idx)) - continue; - - hwc = &event->hw; - armpmu_event_update(event); - perf_sample_data_init(&data, 0, hwc->last_period); - if (!armpmu_event_set_period(event)) - continue; - - if (perf_event_overflow(event, &data, regs)) - cpu_pmu->disable(event); - } - - /* - * Handle the pending perf events. - * - * Note: this call *must* be run with interrupts disabled. For - * platforms that can have the PMU interrupts raised as an NMI, this - * will not work. - */ - irq_work_run(); - - return IRQ_HANDLED; -} - -static void armv7pmu_start(struct arm_pmu *cpu_pmu) -{ - /* Enable all counters */ - armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); -} - -static void armv7pmu_stop(struct arm_pmu *cpu_pmu) -{ - /* Disable all counters */ - armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); -} - -static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - int idx; - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); - struct hw_perf_event *hwc = &event->hw; - unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT; - - /* Always place a cycle counter into the cycle counter. */ - if (evtype == ARMV7_PERFCTR_CPU_CYCLES) { - if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask)) - return -EAGAIN; - - return ARMV7_IDX_CYCLE_COUNTER; - } - - /* - * For anything other than a cycle counter, try and use - * the events counters - */ - for (idx = ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) { - if (!test_and_set_bit(idx, cpuc->used_mask)) - return idx; - } - - /* The counters are all in use. */ - return -EAGAIN; -} - -static void armv7pmu_clear_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - clear_bit(event->hw.idx, cpuc->used_mask); -} - -/* - * Add an event filter to a given event. This will only work for PMUv2 PMUs. - */ -static int armv7pmu_set_event_filter(struct hw_perf_event *event, - struct perf_event_attr *attr) -{ - unsigned long config_base = 0; - - if (attr->exclude_idle) { - pr_debug("ARM performance counters do not support mode exclusion\n"); - return -EOPNOTSUPP; - } - if (attr->exclude_user) - config_base |= ARMV7_EXCLUDE_USER; - if (attr->exclude_kernel) - config_base |= ARMV7_EXCLUDE_PL1; - if (!attr->exclude_hv) - config_base |= ARMV7_INCLUDE_HYP; - - /* - * Install the filter into config_base as this is used to - * construct the event type. - */ - event->config_base = config_base; - - return 0; -} - -static void armv7pmu_reset(void *info) -{ - struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; - u32 idx, nb_cnt = cpu_pmu->num_events, val; - - if (cpu_pmu->secure_access) { - asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); - val |= ARMV7_SDER_SUNIDEN; - asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); - } - - /* The counter and interrupt enable registers are unknown at reset. */ - for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { - armv7_pmnc_disable_counter(idx); - armv7_pmnc_disable_intens(idx); - } - - /* Initialize & Reset PMNC: C and P bits */ - armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); -} - -static int armv7_a8_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &armv7_a8_perf_map, - &armv7_a8_perf_cache_map, 0xFF); -} - -static int armv7_a9_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &armv7_a9_perf_map, - &armv7_a9_perf_cache_map, 0xFF); -} - -static int armv7_a5_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &armv7_a5_perf_map, - &armv7_a5_perf_cache_map, 0xFF); -} - -static int armv7_a15_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &armv7_a15_perf_map, - &armv7_a15_perf_cache_map, 0xFF); -} - -static int armv7_a7_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &armv7_a7_perf_map, - &armv7_a7_perf_cache_map, 0xFF); -} - -static int armv7_a12_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &armv7_a12_perf_map, - &armv7_a12_perf_cache_map, 0xFF); -} - -static int krait_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &krait_perf_map, - &krait_perf_cache_map, 0xFFFFF); -} - -static int krait_map_event_no_branch(struct perf_event *event) -{ - return armpmu_map_event(event, &krait_perf_map_no_branch, - &krait_perf_cache_map, 0xFFFFF); -} - -static int scorpion_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &scorpion_perf_map, - &scorpion_perf_cache_map, 0xFFFFF); -} - -static void armv7pmu_init(struct arm_pmu *cpu_pmu) -{ - cpu_pmu->handle_irq = armv7pmu_handle_irq; - cpu_pmu->enable = armv7pmu_enable_event; - cpu_pmu->disable = armv7pmu_disable_event; - cpu_pmu->read_counter = armv7pmu_read_counter; - cpu_pmu->write_counter = armv7pmu_write_counter; - cpu_pmu->get_event_idx = armv7pmu_get_event_idx; - cpu_pmu->clear_event_idx = armv7pmu_clear_event_idx; - cpu_pmu->start = armv7pmu_start; - cpu_pmu->stop = armv7pmu_stop; - cpu_pmu->reset = armv7pmu_reset; -}; - -static void armv7_read_num_pmnc_events(void *info) -{ - int *nb_cnt = info; - - /* Read the nb of CNTx counters supported from PMNC */ - *nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; - - /* Add the CPU cycles counter */ - *nb_cnt += 1; -} - -static int armv7_probe_num_events(struct arm_pmu *arm_pmu) -{ - return smp_call_function_any(&arm_pmu->supported_cpus, - armv7_read_num_pmnc_events, - &arm_pmu->num_events, 1); -} - -static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_cortex_a8"; - cpu_pmu->map_event = armv7_a8_map_event; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = - &armv7_pmuv1_events_attr_group; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = - &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); -} - -static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_cortex_a9"; - cpu_pmu->map_event = armv7_a9_map_event; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = - &armv7_pmuv1_events_attr_group; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = - &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); -} - -static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_cortex_a5"; - cpu_pmu->map_event = armv7_a5_map_event; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = - &armv7_pmuv1_events_attr_group; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = - &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); -} - -static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_cortex_a15"; - cpu_pmu->map_event = armv7_a15_map_event; - cpu_pmu->set_event_filter = armv7pmu_set_event_filter; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = - &armv7_pmuv2_events_attr_group; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = - &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); -} - -static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_cortex_a7"; - cpu_pmu->map_event = armv7_a7_map_event; - cpu_pmu->set_event_filter = armv7pmu_set_event_filter; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = - &armv7_pmuv2_events_attr_group; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = - &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); -} - -static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_cortex_a12"; - cpu_pmu->map_event = armv7_a12_map_event; - cpu_pmu->set_event_filter = armv7pmu_set_event_filter; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = - &armv7_pmuv2_events_attr_group; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = - &armv7_pmu_format_attr_group; - return armv7_probe_num_events(cpu_pmu); -} - -static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) -{ - int ret = armv7_a12_pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_cortex_a17"; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = - &armv7_pmuv2_events_attr_group; - cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = - &armv7_pmu_format_attr_group; - return ret; -} - -/* - * Krait Performance Monitor Region Event Selection Register (PMRESRn) - * - * 31 30 24 16 8 0 - * +--------------------------------+ - * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0 - * +--------------------------------+ - * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1 - * +--------------------------------+ - * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2 - * +--------------------------------+ - * VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ? - * +--------------------------------+ - * EN | G=3 | G=2 | G=1 | G=0 - * - * Event Encoding: - * - * hwc->config_base = 0xNRCCG - * - * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR) - * R = region register - * CC = class of events the group G is choosing from - * G = group or particular event - * - * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2 - * - * A region (R) corresponds to a piece of the CPU (execution unit, instruction - * unit, etc.) while the event code (CC) corresponds to a particular class of - * events (interrupts for example). An event code is broken down into - * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for - * example). - */ - -#define KRAIT_EVENT (1 << 16) -#define VENUM_EVENT (2 << 16) -#define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT) -#define PMRESRn_EN BIT(31) - -#define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */ -#define EVENT_GROUP(event) ((event) & 0xf) /* G */ -#define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */ -#define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */ -#define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */ - -static u32 krait_read_pmresrn(int n) -{ - u32 val; - - switch (n) { - case 0: - asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); - break; - case 1: - asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); - break; - case 2: - asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); - break; - default: - BUG(); /* Should be validated in krait_pmu_get_event_idx() */ - } - - return val; -} - -static void krait_write_pmresrn(int n, u32 val) -{ - switch (n) { - case 0: - asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); - break; - case 1: - asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); - break; - case 2: - asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); - break; - default: - BUG(); /* Should be validated in krait_pmu_get_event_idx() */ - } -} - -static u32 venum_read_pmresr(void) -{ - u32 val; - asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); - return val; -} - -static void venum_write_pmresr(u32 val) -{ - asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); -} - -static void venum_pre_pmresr(u32 *venum_orig_val, u32 *fp_orig_val) -{ - u32 venum_new_val; - u32 fp_new_val; - - BUG_ON(preemptible()); - /* CPACR Enable CP10 and CP11 access */ - *venum_orig_val = get_copro_access(); - venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11); - set_copro_access(venum_new_val); - - /* Enable FPEXC */ - *fp_orig_val = fmrx(FPEXC); - fp_new_val = *fp_orig_val | FPEXC_EN; - fmxr(FPEXC, fp_new_val); -} - -static void venum_post_pmresr(u32 venum_orig_val, u32 fp_orig_val) -{ - BUG_ON(preemptible()); - /* Restore FPEXC */ - fmxr(FPEXC, fp_orig_val); - isb(); - /* Restore CPACR */ - set_copro_access(venum_orig_val); -} - -static u32 krait_get_pmresrn_event(unsigned int region) -{ - static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0, - KRAIT_PMRESR1_GROUP0, - KRAIT_PMRESR2_GROUP0 }; - return pmresrn_table[region]; -} - -static void krait_evt_setup(int idx, u32 config_base) -{ - u32 val; - u32 mask; - u32 vval, fval; - unsigned int region = EVENT_REGION(config_base); - unsigned int group = EVENT_GROUP(config_base); - unsigned int code = EVENT_CODE(config_base); - unsigned int group_shift; - bool venum_event = EVENT_VENUM(config_base); - - group_shift = group * 8; - mask = 0xff << group_shift; - - /* Configure evtsel for the region and group */ - if (venum_event) - val = KRAIT_VPMRESR0_GROUP0; - else - val = krait_get_pmresrn_event(region); - val += group; - /* Mix in mode-exclusion bits */ - val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); - armv7_pmnc_write_evtsel(idx, val); - - if (venum_event) { - venum_pre_pmresr(&vval, &fval); - val = venum_read_pmresr(); - val &= ~mask; - val |= code << group_shift; - val |= PMRESRn_EN; - venum_write_pmresr(val); - venum_post_pmresr(vval, fval); - } else { - val = krait_read_pmresrn(region); - val &= ~mask; - val |= code << group_shift; - val |= PMRESRn_EN; - krait_write_pmresrn(region, val); - } -} - -static u32 clear_pmresrn_group(u32 val, int group) -{ - u32 mask; - int group_shift; - - group_shift = group * 8; - mask = 0xff << group_shift; - val &= ~mask; - - /* Don't clear enable bit if entire region isn't disabled */ - if (val & ~PMRESRn_EN) - return val |= PMRESRn_EN; - - return 0; -} - -static void krait_clearpmu(u32 config_base) -{ - u32 val; - u32 vval, fval; - unsigned int region = EVENT_REGION(config_base); - unsigned int group = EVENT_GROUP(config_base); - bool venum_event = EVENT_VENUM(config_base); - - if (venum_event) { - venum_pre_pmresr(&vval, &fval); - val = venum_read_pmresr(); - val = clear_pmresrn_group(val, group); - venum_write_pmresr(val); - venum_post_pmresr(vval, fval); - } else { - val = krait_read_pmresrn(region); - val = clear_pmresrn_group(val, group); - krait_write_pmresrn(region, val); - } -} - -static void krait_pmu_disable_event(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - /* Disable counter and interrupt */ - - /* Disable counter */ - armv7_pmnc_disable_counter(idx); - - /* - * Clear pmresr code (if destined for PMNx counters) - */ - if (hwc->config_base & KRAIT_EVENT_MASK) - krait_clearpmu(hwc->config_base); - - /* Disable interrupt for this counter */ - armv7_pmnc_disable_intens(idx); -} - -static void krait_pmu_enable_event(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - /* - * Enable counter and interrupt, and set the counter to count - * the event that we're interested in. - */ - - /* Disable counter */ - armv7_pmnc_disable_counter(idx); - - /* - * Set event (if destined for PMNx counters) - * We set the event for the cycle counter because we - * have the ability to perform event filtering. - */ - if (hwc->config_base & KRAIT_EVENT_MASK) - krait_evt_setup(idx, hwc->config_base); - else - armv7_pmnc_write_evtsel(idx, hwc->config_base); - - /* Enable interrupt for this counter */ - armv7_pmnc_enable_intens(idx); - - /* Enable counter */ - armv7_pmnc_enable_counter(idx); -} - -static void krait_pmu_reset(void *info) -{ - u32 vval, fval; - struct arm_pmu *cpu_pmu = info; - u32 idx, nb_cnt = cpu_pmu->num_events; - - armv7pmu_reset(info); - - /* Clear all pmresrs */ - krait_write_pmresrn(0, 0); - krait_write_pmresrn(1, 0); - krait_write_pmresrn(2, 0); - - venum_pre_pmresr(&vval, &fval); - venum_write_pmresr(0); - venum_post_pmresr(vval, fval); - - /* Reset PMxEVNCTCR to sane default */ - for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { - armv7_pmnc_select_counter(idx); - asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); - } - -} - -static int krait_event_to_bit(struct perf_event *event, unsigned int region, - unsigned int group) -{ - int bit; - struct hw_perf_event *hwc = &event->hw; - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); - - if (hwc->config_base & VENUM_EVENT) - bit = KRAIT_VPMRESR0_GROUP0; - else - bit = krait_get_pmresrn_event(region); - bit -= krait_get_pmresrn_event(0); - bit += group; - /* - * Lower bits are reserved for use by the counters (see - * armv7pmu_get_event_idx() for more info) - */ - bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; - - return bit; -} - -/* - * We check for column exclusion constraints here. - * Two events cant use the same group within a pmresr register. - */ -static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - int idx; - int bit = -1; - struct hw_perf_event *hwc = &event->hw; - unsigned int region = EVENT_REGION(hwc->config_base); - unsigned int code = EVENT_CODE(hwc->config_base); - unsigned int group = EVENT_GROUP(hwc->config_base); - bool venum_event = EVENT_VENUM(hwc->config_base); - bool krait_event = EVENT_CPU(hwc->config_base); - - if (venum_event || krait_event) { - /* Ignore invalid events */ - if (group > 3 || region > 2) - return -EINVAL; - if (venum_event && (code & 0xe0)) - return -EINVAL; - - bit = krait_event_to_bit(event, region, group); - if (test_and_set_bit(bit, cpuc->used_mask)) - return -EAGAIN; - } - - idx = armv7pmu_get_event_idx(cpuc, event); - if (idx < 0 && bit >= 0) - clear_bit(bit, cpuc->used_mask); - - return idx; -} - -static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - int bit; - struct hw_perf_event *hwc = &event->hw; - unsigned int region = EVENT_REGION(hwc->config_base); - unsigned int group = EVENT_GROUP(hwc->config_base); - bool venum_event = EVENT_VENUM(hwc->config_base); - bool krait_event = EVENT_CPU(hwc->config_base); - - armv7pmu_clear_event_idx(cpuc, event); - if (venum_event || krait_event) { - bit = krait_event_to_bit(event, region, group); - clear_bit(bit, cpuc->used_mask); - } -} - -static int krait_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_krait"; - /* Some early versions of Krait don't support PC write events */ - if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node, - "qcom,no-pc-write")) - cpu_pmu->map_event = krait_map_event_no_branch; - else - cpu_pmu->map_event = krait_map_event; - cpu_pmu->set_event_filter = armv7pmu_set_event_filter; - cpu_pmu->reset = krait_pmu_reset; - cpu_pmu->enable = krait_pmu_enable_event; - cpu_pmu->disable = krait_pmu_disable_event; - cpu_pmu->get_event_idx = krait_pmu_get_event_idx; - cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx; - return armv7_probe_num_events(cpu_pmu); -} - -/* - * Scorpion Local Performance Monitor Register (LPMn) - * - * 31 30 24 16 8 0 - * +--------------------------------+ - * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0 - * +--------------------------------+ - * LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1 - * +--------------------------------+ - * LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2 - * +--------------------------------+ - * L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3 - * +--------------------------------+ - * VLPM | EN | CC | CC | CC | CC | N = 2, R = ? - * +--------------------------------+ - * EN | G=3 | G=2 | G=1 | G=0 - * - * - * Event Encoding: - * - * hwc->config_base = 0xNRCCG - * - * N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM) - * R = region register - * CC = class of events the group G is choosing from - * G = group or particular event - * - * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2 - * - * A region (R) corresponds to a piece of the CPU (execution unit, instruction - * unit, etc.) while the event code (CC) corresponds to a particular class of - * events (interrupts for example). An event code is broken down into - * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for - * example). - */ - -static u32 scorpion_read_pmresrn(int n) -{ - u32 val; - - switch (n) { - case 0: - asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); - break; - case 1: - asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); - break; - case 2: - asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); - break; - case 3: - asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); - break; - default: - BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ - } - - return val; -} - -static void scorpion_write_pmresrn(int n, u32 val) -{ - switch (n) { - case 0: - asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); - break; - case 1: - asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); - break; - case 2: - asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); - break; - case 3: - asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); - break; - default: - BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ - } -} - -static u32 scorpion_get_pmresrn_event(unsigned int region) -{ - static const u32 pmresrn_table[] = { SCORPION_LPM0_GROUP0, - SCORPION_LPM1_GROUP0, - SCORPION_LPM2_GROUP0, - SCORPION_L2LPM_GROUP0 }; - return pmresrn_table[region]; -} - -static void scorpion_evt_setup(int idx, u32 config_base) -{ - u32 val; - u32 mask; - u32 vval, fval; - unsigned int region = EVENT_REGION(config_base); - unsigned int group = EVENT_GROUP(config_base); - unsigned int code = EVENT_CODE(config_base); - unsigned int group_shift; - bool venum_event = EVENT_VENUM(config_base); - - group_shift = group * 8; - mask = 0xff << group_shift; - - /* Configure evtsel for the region and group */ - if (venum_event) - val = SCORPION_VLPM_GROUP0; - else - val = scorpion_get_pmresrn_event(region); - val += group; - /* Mix in mode-exclusion bits */ - val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); - armv7_pmnc_write_evtsel(idx, val); - - asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); - - if (venum_event) { - venum_pre_pmresr(&vval, &fval); - val = venum_read_pmresr(); - val &= ~mask; - val |= code << group_shift; - val |= PMRESRn_EN; - venum_write_pmresr(val); - venum_post_pmresr(vval, fval); - } else { - val = scorpion_read_pmresrn(region); - val &= ~mask; - val |= code << group_shift; - val |= PMRESRn_EN; - scorpion_write_pmresrn(region, val); - } -} - -static void scorpion_clearpmu(u32 config_base) -{ - u32 val; - u32 vval, fval; - unsigned int region = EVENT_REGION(config_base); - unsigned int group = EVENT_GROUP(config_base); - bool venum_event = EVENT_VENUM(config_base); - - if (venum_event) { - venum_pre_pmresr(&vval, &fval); - val = venum_read_pmresr(); - val = clear_pmresrn_group(val, group); - venum_write_pmresr(val); - venum_post_pmresr(vval, fval); - } else { - val = scorpion_read_pmresrn(region); - val = clear_pmresrn_group(val, group); - scorpion_write_pmresrn(region, val); - } -} - -static void scorpion_pmu_disable_event(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - /* Disable counter and interrupt */ - - /* Disable counter */ - armv7_pmnc_disable_counter(idx); - - /* - * Clear pmresr code (if destined for PMNx counters) - */ - if (hwc->config_base & KRAIT_EVENT_MASK) - scorpion_clearpmu(hwc->config_base); - - /* Disable interrupt for this counter */ - armv7_pmnc_disable_intens(idx); -} - -static void scorpion_pmu_enable_event(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - /* - * Enable counter and interrupt, and set the counter to count - * the event that we're interested in. - */ - - /* Disable counter */ - armv7_pmnc_disable_counter(idx); - - /* - * Set event (if destined for PMNx counters) - * We don't set the event for the cycle counter because we - * don't have the ability to perform event filtering. - */ - if (hwc->config_base & KRAIT_EVENT_MASK) - scorpion_evt_setup(idx, hwc->config_base); - else if (idx != ARMV7_IDX_CYCLE_COUNTER) - armv7_pmnc_write_evtsel(idx, hwc->config_base); - - /* Enable interrupt for this counter */ - armv7_pmnc_enable_intens(idx); - - /* Enable counter */ - armv7_pmnc_enable_counter(idx); -} - -static void scorpion_pmu_reset(void *info) -{ - u32 vval, fval; - struct arm_pmu *cpu_pmu = info; - u32 idx, nb_cnt = cpu_pmu->num_events; - - armv7pmu_reset(info); - - /* Clear all pmresrs */ - scorpion_write_pmresrn(0, 0); - scorpion_write_pmresrn(1, 0); - scorpion_write_pmresrn(2, 0); - scorpion_write_pmresrn(3, 0); - - venum_pre_pmresr(&vval, &fval); - venum_write_pmresr(0); - venum_post_pmresr(vval, fval); - - /* Reset PMxEVNCTCR to sane default */ - for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) { - armv7_pmnc_select_counter(idx); - asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); - } -} - -static int scorpion_event_to_bit(struct perf_event *event, unsigned int region, - unsigned int group) -{ - int bit; - struct hw_perf_event *hwc = &event->hw; - struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); - - if (hwc->config_base & VENUM_EVENT) - bit = SCORPION_VLPM_GROUP0; - else - bit = scorpion_get_pmresrn_event(region); - bit -= scorpion_get_pmresrn_event(0); - bit += group; - /* - * Lower bits are reserved for use by the counters (see - * armv7pmu_get_event_idx() for more info) - */ - bit += ARMV7_IDX_COUNTER_LAST(cpu_pmu) + 1; - - return bit; -} - -/* - * We check for column exclusion constraints here. - * Two events cant use the same group within a pmresr register. - */ -static int scorpion_pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - int idx; - int bit = -1; - struct hw_perf_event *hwc = &event->hw; - unsigned int region = EVENT_REGION(hwc->config_base); - unsigned int group = EVENT_GROUP(hwc->config_base); - bool venum_event = EVENT_VENUM(hwc->config_base); - bool scorpion_event = EVENT_CPU(hwc->config_base); - - if (venum_event || scorpion_event) { - /* Ignore invalid events */ - if (group > 3 || region > 3) - return -EINVAL; - - bit = scorpion_event_to_bit(event, region, group); - if (test_and_set_bit(bit, cpuc->used_mask)) - return -EAGAIN; - } - - idx = armv7pmu_get_event_idx(cpuc, event); - if (idx < 0 && bit >= 0) - clear_bit(bit, cpuc->used_mask); - - return idx; -} - -static void scorpion_pmu_clear_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - int bit; - struct hw_perf_event *hwc = &event->hw; - unsigned int region = EVENT_REGION(hwc->config_base); - unsigned int group = EVENT_GROUP(hwc->config_base); - bool venum_event = EVENT_VENUM(hwc->config_base); - bool scorpion_event = EVENT_CPU(hwc->config_base); - - armv7pmu_clear_event_idx(cpuc, event); - if (venum_event || scorpion_event) { - bit = scorpion_event_to_bit(event, region, group); - clear_bit(bit, cpuc->used_mask); - } -} - -static int scorpion_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_scorpion"; - cpu_pmu->map_event = scorpion_map_event; - cpu_pmu->reset = scorpion_pmu_reset; - cpu_pmu->enable = scorpion_pmu_enable_event; - cpu_pmu->disable = scorpion_pmu_disable_event; - cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; - cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; - return armv7_probe_num_events(cpu_pmu); -} - -static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu) -{ - armv7pmu_init(cpu_pmu); - cpu_pmu->name = "armv7_scorpion_mp"; - cpu_pmu->map_event = scorpion_map_event; - cpu_pmu->reset = scorpion_pmu_reset; - cpu_pmu->enable = scorpion_pmu_enable_event; - cpu_pmu->disable = scorpion_pmu_disable_event; - cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; - cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; - return armv7_probe_num_events(cpu_pmu); -} - -static const struct of_device_id armv7_pmu_of_device_ids[] = { - {.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init}, - {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, - {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init}, - {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, - {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, - {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, - {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, - {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, - {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init}, - {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init}, - {}, -}; - -static const struct pmu_probe_info armv7_pmu_probe_table[] = { - ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A8, armv7_a8_pmu_init), - ARM_PMU_PROBE(ARM_CPU_PART_CORTEX_A9, armv7_a9_pmu_init), - { /* sentinel value */ } -}; - - -static int armv7_pmu_device_probe(struct platform_device *pdev) -{ - return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids, - armv7_pmu_probe_table); -} - -static struct platform_driver armv7_pmu_driver = { - .driver = { - .name = "armv7-pmu", - .of_match_table = armv7_pmu_of_device_ids, - .suppress_bind_attrs = true, - }, - .probe = armv7_pmu_device_probe, -}; - -builtin_platform_driver(armv7_pmu_driver); -#endif /* CONFIG_CPU_V7 */ diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c deleted file mode 100644 index 7a2ba1c689a7..000000000000 --- a/arch/arm/kernel/perf_event_xscale.c +++ /dev/null @@ -1,748 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * ARMv5 [xscale] Performance counter handling code. - * - * Copyright (C) 2010, ARM Ltd., Will Deacon <will.deacon@arm.com> - * - * Based on the previous xscale OProfile code. - * - * There are two variants of the xscale PMU that we support: - * - xscale1pmu: 2 event counters and a cycle counter - * - xscale2pmu: 4 event counters and a cycle counter - * The two variants share event definitions, but have different - * PMU structures. - */ - -#ifdef CONFIG_CPU_XSCALE - -#include <asm/cputype.h> -#include <asm/irq_regs.h> - -#include <linux/of.h> -#include <linux/perf/arm_pmu.h> -#include <linux/platform_device.h> - -enum xscale_perf_types { - XSCALE_PERFCTR_ICACHE_MISS = 0x00, - XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01, - XSCALE_PERFCTR_DATA_STALL = 0x02, - XSCALE_PERFCTR_ITLB_MISS = 0x03, - XSCALE_PERFCTR_DTLB_MISS = 0x04, - XSCALE_PERFCTR_BRANCH = 0x05, - XSCALE_PERFCTR_BRANCH_MISS = 0x06, - XSCALE_PERFCTR_INSTRUCTION = 0x07, - XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08, - XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09, - XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A, - XSCALE_PERFCTR_DCACHE_MISS = 0x0B, - XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C, - XSCALE_PERFCTR_PC_CHANGED = 0x0D, - XSCALE_PERFCTR_BCU_REQUEST = 0x10, - XSCALE_PERFCTR_BCU_FULL = 0x11, - XSCALE_PERFCTR_BCU_DRAIN = 0x12, - XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14, - XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15, - XSCALE_PERFCTR_RMW = 0x16, - /* XSCALE_PERFCTR_CCNT is not hardware defined */ - XSCALE_PERFCTR_CCNT = 0xFE, - XSCALE_PERFCTR_UNUSED = 0xFF, -}; - -enum xscale_counters { - XSCALE_CYCLE_COUNTER = 0, - XSCALE_COUNTER0, - XSCALE_COUNTER1, - XSCALE_COUNTER2, - XSCALE_COUNTER3, -}; - -static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = { - PERF_MAP_ALL_UNSUPPORTED, - [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT, - [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION, - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH, - [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS, - [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = XSCALE_PERFCTR_ICACHE_NO_DELIVER, -}; - -static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] - [PERF_COUNT_HW_CACHE_OP_MAX] - [PERF_COUNT_HW_CACHE_RESULT_MAX] = { - PERF_CACHE_MAP_ALL_UNSUPPORTED, - - [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, - [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, - [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS, - [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS, - - [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS, - - [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, - [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS, - - [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, - [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS, -}; - -#define XSCALE_PMU_ENABLE 0x001 -#define XSCALE_PMN_RESET 0x002 -#define XSCALE_CCNT_RESET 0x004 -#define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET) -#define XSCALE_PMU_CNT64 0x008 - -#define XSCALE1_OVERFLOWED_MASK 0x700 -#define XSCALE1_CCOUNT_OVERFLOW 0x400 -#define XSCALE1_COUNT0_OVERFLOW 0x100 -#define XSCALE1_COUNT1_OVERFLOW 0x200 -#define XSCALE1_CCOUNT_INT_EN 0x040 -#define XSCALE1_COUNT0_INT_EN 0x010 -#define XSCALE1_COUNT1_INT_EN 0x020 -#define XSCALE1_COUNT0_EVT_SHFT 12 -#define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT) -#define XSCALE1_COUNT1_EVT_SHFT 20 -#define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT) - -static inline u32 -xscale1pmu_read_pmnc(void) -{ - u32 val; - asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val)); - return val; -} - -static inline void -xscale1pmu_write_pmnc(u32 val) -{ - /* upper 4bits and 7, 11 are write-as-0 */ - val &= 0xffff77f; - asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val)); -} - -static inline int -xscale1_pmnc_counter_has_overflowed(unsigned long pmnc, - enum xscale_counters counter) -{ - int ret = 0; - - switch (counter) { - case XSCALE_CYCLE_COUNTER: - ret = pmnc & XSCALE1_CCOUNT_OVERFLOW; - break; - case XSCALE_COUNTER0: - ret = pmnc & XSCALE1_COUNT0_OVERFLOW; - break; - case XSCALE_COUNTER1: - ret = pmnc & XSCALE1_COUNT1_OVERFLOW; - break; - default: - WARN_ONCE(1, "invalid counter number (%d)\n", counter); - } - - return ret; -} - -static irqreturn_t -xscale1pmu_handle_irq(struct arm_pmu *cpu_pmu) -{ - unsigned long pmnc; - struct perf_sample_data data; - struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); - struct pt_regs *regs; - int idx; - - /* - * NOTE: there's an A stepping erratum that states if an overflow - * bit already exists and another occurs, the previous - * Overflow bit gets cleared. There's no workaround. - * Fixed in B stepping or later. - */ - pmnc = xscale1pmu_read_pmnc(); - - /* - * Write the value back to clear the overflow flags. Overflow - * flags remain in pmnc for use below. We also disable the PMU - * while we process the interrupt. - */ - xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); - - if (!(pmnc & XSCALE1_OVERFLOWED_MASK)) - return IRQ_NONE; - - regs = get_irq_regs(); - - for (idx = 0; idx < cpu_pmu->num_events; ++idx) { - struct perf_event *event = cpuc->events[idx]; - struct hw_perf_event *hwc; - - if (!event) - continue; - - if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) - continue; - - hwc = &event->hw; - armpmu_event_update(event); - perf_sample_data_init(&data, 0, hwc->last_period); - if (!armpmu_event_set_period(event)) - continue; - - if (perf_event_overflow(event, &data, regs)) - cpu_pmu->disable(event); - } - - irq_work_run(); - - /* - * Re-enable the PMU. - */ - pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE; - xscale1pmu_write_pmnc(pmnc); - - return IRQ_HANDLED; -} - -static void xscale1pmu_enable_event(struct perf_event *event) -{ - unsigned long val, mask, evt; - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - switch (idx) { - case XSCALE_CYCLE_COUNTER: - mask = 0; - evt = XSCALE1_CCOUNT_INT_EN; - break; - case XSCALE_COUNTER0: - mask = XSCALE1_COUNT0_EVT_MASK; - evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) | - XSCALE1_COUNT0_INT_EN; - break; - case XSCALE_COUNTER1: - mask = XSCALE1_COUNT1_EVT_MASK; - evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) | - XSCALE1_COUNT1_INT_EN; - break; - default: - WARN_ONCE(1, "invalid counter number (%d)\n", idx); - return; - } - - val = xscale1pmu_read_pmnc(); - val &= ~mask; - val |= evt; - xscale1pmu_write_pmnc(val); -} - -static void xscale1pmu_disable_event(struct perf_event *event) -{ - unsigned long val, mask, evt; - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - switch (idx) { - case XSCALE_CYCLE_COUNTER: - mask = XSCALE1_CCOUNT_INT_EN; - evt = 0; - break; - case XSCALE_COUNTER0: - mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK; - evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT; - break; - case XSCALE_COUNTER1: - mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK; - evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT; - break; - default: - WARN_ONCE(1, "invalid counter number (%d)\n", idx); - return; - } - - val = xscale1pmu_read_pmnc(); - val &= ~mask; - val |= evt; - xscale1pmu_write_pmnc(val); -} - -static int -xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - if (XSCALE_PERFCTR_CCNT == hwc->config_base) { - if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask)) - return -EAGAIN; - - return XSCALE_CYCLE_COUNTER; - } else { - if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) - return XSCALE_COUNTER1; - - if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) - return XSCALE_COUNTER0; - - return -EAGAIN; - } -} - -static void xscalepmu_clear_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - clear_bit(event->hw.idx, cpuc->used_mask); -} - -static void xscale1pmu_start(struct arm_pmu *cpu_pmu) -{ - unsigned long val; - - val = xscale1pmu_read_pmnc(); - val |= XSCALE_PMU_ENABLE; - xscale1pmu_write_pmnc(val); -} - -static void xscale1pmu_stop(struct arm_pmu *cpu_pmu) -{ - unsigned long val; - - val = xscale1pmu_read_pmnc(); - val &= ~XSCALE_PMU_ENABLE; - xscale1pmu_write_pmnc(val); -} - -static inline u64 xscale1pmu_read_counter(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - int counter = hwc->idx; - u32 val = 0; - - switch (counter) { - case XSCALE_CYCLE_COUNTER: - asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val)); - break; - case XSCALE_COUNTER0: - asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val)); - break; - case XSCALE_COUNTER1: - asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val)); - break; - } - - return val; -} - -static inline void xscale1pmu_write_counter(struct perf_event *event, u64 val) -{ - struct hw_perf_event *hwc = &event->hw; - int counter = hwc->idx; - - switch (counter) { - case XSCALE_CYCLE_COUNTER: - asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val)); - break; - case XSCALE_COUNTER0: - asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val)); - break; - case XSCALE_COUNTER1: - asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val)); - break; - } -} - -static int xscale_map_event(struct perf_event *event) -{ - return armpmu_map_event(event, &xscale_perf_map, - &xscale_perf_cache_map, 0xFF); -} - -static int xscale1pmu_init(struct arm_pmu *cpu_pmu) -{ - cpu_pmu->name = "armv5_xscale1"; - cpu_pmu->handle_irq = xscale1pmu_handle_irq; - cpu_pmu->enable = xscale1pmu_enable_event; - cpu_pmu->disable = xscale1pmu_disable_event; - cpu_pmu->read_counter = xscale1pmu_read_counter; - cpu_pmu->write_counter = xscale1pmu_write_counter; - cpu_pmu->get_event_idx = xscale1pmu_get_event_idx; - cpu_pmu->clear_event_idx = xscalepmu_clear_event_idx; - cpu_pmu->start = xscale1pmu_start; - cpu_pmu->stop = xscale1pmu_stop; - cpu_pmu->map_event = xscale_map_event; - cpu_pmu->num_events = 3; - - return 0; -} - -#define XSCALE2_OVERFLOWED_MASK 0x01f -#define XSCALE2_CCOUNT_OVERFLOW 0x001 -#define XSCALE2_COUNT0_OVERFLOW 0x002 -#define XSCALE2_COUNT1_OVERFLOW 0x004 -#define XSCALE2_COUNT2_OVERFLOW 0x008 -#define XSCALE2_COUNT3_OVERFLOW 0x010 -#define XSCALE2_CCOUNT_INT_EN 0x001 -#define XSCALE2_COUNT0_INT_EN 0x002 -#define XSCALE2_COUNT1_INT_EN 0x004 -#define XSCALE2_COUNT2_INT_EN 0x008 -#define XSCALE2_COUNT3_INT_EN 0x010 -#define XSCALE2_COUNT0_EVT_SHFT 0 -#define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT) -#define XSCALE2_COUNT1_EVT_SHFT 8 -#define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT) -#define XSCALE2_COUNT2_EVT_SHFT 16 -#define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT) -#define XSCALE2_COUNT3_EVT_SHFT 24 -#define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT) - -static inline u32 -xscale2pmu_read_pmnc(void) -{ - u32 val; - asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val)); - /* bits 1-2 and 4-23 are read-unpredictable */ - return val & 0xff000009; -} - -static inline void -xscale2pmu_write_pmnc(u32 val) -{ - /* bits 4-23 are write-as-0, 24-31 are write ignored */ - val &= 0xf; - asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val)); -} - -static inline u32 -xscale2pmu_read_overflow_flags(void) -{ - u32 val; - asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val)); - return val; -} - -static inline void -xscale2pmu_write_overflow_flags(u32 val) -{ - asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val)); -} - -static inline u32 -xscale2pmu_read_event_select(void) -{ - u32 val; - asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val)); - return val; -} - -static inline void -xscale2pmu_write_event_select(u32 val) -{ - asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val)); -} - -static inline u32 -xscale2pmu_read_int_enable(void) -{ - u32 val; - asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val)); - return val; -} - -static void -xscale2pmu_write_int_enable(u32 val) -{ - asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val)); -} - -static inline int -xscale2_pmnc_counter_has_overflowed(unsigned long of_flags, - enum xscale_counters counter) -{ - int ret = 0; - - switch (counter) { - case XSCALE_CYCLE_COUNTER: - ret = of_flags & XSCALE2_CCOUNT_OVERFLOW; - break; - case XSCALE_COUNTER0: - ret = of_flags & XSCALE2_COUNT0_OVERFLOW; - break; - case XSCALE_COUNTER1: - ret = of_flags & XSCALE2_COUNT1_OVERFLOW; - break; - case XSCALE_COUNTER2: - ret = of_flags & XSCALE2_COUNT2_OVERFLOW; - break; - case XSCALE_COUNTER3: - ret = of_flags & XSCALE2_COUNT3_OVERFLOW; - break; - default: - WARN_ONCE(1, "invalid counter number (%d)\n", counter); - } - - return ret; -} - -static irqreturn_t -xscale2pmu_handle_irq(struct arm_pmu *cpu_pmu) -{ - unsigned long pmnc, of_flags; - struct perf_sample_data data; - struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); - struct pt_regs *regs; - int idx; - - /* Disable the PMU. */ - pmnc = xscale2pmu_read_pmnc(); - xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE); - - /* Check the overflow flag register. */ - of_flags = xscale2pmu_read_overflow_flags(); - if (!(of_flags & XSCALE2_OVERFLOWED_MASK)) - return IRQ_NONE; - - /* Clear the overflow bits. */ - xscale2pmu_write_overflow_flags(of_flags); - - regs = get_irq_regs(); - - for (idx = 0; idx < cpu_pmu->num_events; ++idx) { - struct perf_event *event = cpuc->events[idx]; - struct hw_perf_event *hwc; - - if (!event) - continue; - - if (!xscale2_pmnc_counter_has_overflowed(of_flags, idx)) - continue; - - hwc = &event->hw; - armpmu_event_update(event); - perf_sample_data_init(&data, 0, hwc->last_period); - if (!armpmu_event_set_period(event)) - continue; - - if (perf_event_overflow(event, &data, regs)) - cpu_pmu->disable(event); - } - - irq_work_run(); - - /* - * Re-enable the PMU. - */ - pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE; - xscale2pmu_write_pmnc(pmnc); - - return IRQ_HANDLED; -} - -static void xscale2pmu_enable_event(struct perf_event *event) -{ - unsigned long ien, evtsel; - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - ien = xscale2pmu_read_int_enable(); - evtsel = xscale2pmu_read_event_select(); - - switch (idx) { - case XSCALE_CYCLE_COUNTER: - ien |= XSCALE2_CCOUNT_INT_EN; - break; - case XSCALE_COUNTER0: - ien |= XSCALE2_COUNT0_INT_EN; - evtsel &= ~XSCALE2_COUNT0_EVT_MASK; - evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT; - break; - case XSCALE_COUNTER1: - ien |= XSCALE2_COUNT1_INT_EN; - evtsel &= ~XSCALE2_COUNT1_EVT_MASK; - evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT; - break; - case XSCALE_COUNTER2: - ien |= XSCALE2_COUNT2_INT_EN; - evtsel &= ~XSCALE2_COUNT2_EVT_MASK; - evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT; - break; - case XSCALE_COUNTER3: - ien |= XSCALE2_COUNT3_INT_EN; - evtsel &= ~XSCALE2_COUNT3_EVT_MASK; - evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT; - break; - default: - WARN_ONCE(1, "invalid counter number (%d)\n", idx); - return; - } - - xscale2pmu_write_event_select(evtsel); - xscale2pmu_write_int_enable(ien); -} - -static void xscale2pmu_disable_event(struct perf_event *event) -{ - unsigned long ien, evtsel, of_flags; - struct hw_perf_event *hwc = &event->hw; - int idx = hwc->idx; - - ien = xscale2pmu_read_int_enable(); - evtsel = xscale2pmu_read_event_select(); - - switch (idx) { - case XSCALE_CYCLE_COUNTER: - ien &= ~XSCALE2_CCOUNT_INT_EN; - of_flags = XSCALE2_CCOUNT_OVERFLOW; - break; - case XSCALE_COUNTER0: - ien &= ~XSCALE2_COUNT0_INT_EN; - evtsel &= ~XSCALE2_COUNT0_EVT_MASK; - evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT; - of_flags = XSCALE2_COUNT0_OVERFLOW; - break; - case XSCALE_COUNTER1: - ien &= ~XSCALE2_COUNT1_INT_EN; - evtsel &= ~XSCALE2_COUNT1_EVT_MASK; - evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT; - of_flags = XSCALE2_COUNT1_OVERFLOW; - break; - case XSCALE_COUNTER2: - ien &= ~XSCALE2_COUNT2_INT_EN; - evtsel &= ~XSCALE2_COUNT2_EVT_MASK; - evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT; - of_flags = XSCALE2_COUNT2_OVERFLOW; - break; - case XSCALE_COUNTER3: - ien &= ~XSCALE2_COUNT3_INT_EN; - evtsel &= ~XSCALE2_COUNT3_EVT_MASK; - evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT; - of_flags = XSCALE2_COUNT3_OVERFLOW; - break; - default: - WARN_ONCE(1, "invalid counter number (%d)\n", idx); - return; - } - - xscale2pmu_write_event_select(evtsel); - xscale2pmu_write_int_enable(ien); - xscale2pmu_write_overflow_flags(of_flags); -} - -static int -xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc, - struct perf_event *event) -{ - int idx = xscale1pmu_get_event_idx(cpuc, event); - if (idx >= 0) - goto out; - - if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask)) - idx = XSCALE_COUNTER3; - else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask)) - idx = XSCALE_COUNTER2; -out: - return idx; -} - -static void xscale2pmu_start(struct arm_pmu *cpu_pmu) -{ - unsigned long val; - - val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; - val |= XSCALE_PMU_ENABLE; - xscale2pmu_write_pmnc(val); -} - -static void xscale2pmu_stop(struct arm_pmu *cpu_pmu) -{ - unsigned long val; - - val = xscale2pmu_read_pmnc(); - val &= ~XSCALE_PMU_ENABLE; - xscale2pmu_write_pmnc(val); -} - -static inline u64 xscale2pmu_read_counter(struct perf_event *event) -{ - struct hw_perf_event *hwc = &event->hw; - int counter = hwc->idx; - u32 val = 0; - - switch (counter) { - case XSCALE_CYCLE_COUNTER: - asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val)); - break; - case XSCALE_COUNTER0: - asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val)); - break; - case XSCALE_COUNTER1: - asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val)); - break; - case XSCALE_COUNTER2: - asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val)); - break; - case XSCALE_COUNTER3: - asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val)); - break; - } - - return val; -} - -static inline void xscale2pmu_write_counter(struct perf_event *event, u64 val) -{ - struct hw_perf_event *hwc = &event->hw; - int counter = hwc->idx; - - switch (counter) { - case XSCALE_CYCLE_COUNTER: - asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val)); - break; - case XSCALE_COUNTER0: - asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val)); - break; - case XSCALE_COUNTER1: - asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val)); - break; - case XSCALE_COUNTER2: - asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val)); - break; - case XSCALE_COUNTER3: - asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val)); - break; - } -} - -static int xscale2pmu_init(struct arm_pmu *cpu_pmu) -{ - cpu_pmu->name = "armv5_xscale2"; - cpu_pmu->handle_irq = xscale2pmu_handle_irq; - cpu_pmu->enable = xscale2pmu_enable_event; - cpu_pmu->disable = xscale2pmu_disable_event; - cpu_pmu->read_counter = xscale2pmu_read_counter; - cpu_pmu->write_counter = xscale2pmu_write_counter; - cpu_pmu->get_event_idx = xscale2pmu_get_event_idx; - cpu_pmu->clear_event_idx = xscalepmu_clear_event_idx; - cpu_pmu->start = xscale2pmu_start; - cpu_pmu->stop = xscale2pmu_stop; - cpu_pmu->map_event = xscale_map_event; - cpu_pmu->num_events = 5; - - return 0; -} - -static const struct pmu_probe_info xscale_pmu_probe_table[] = { - XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V1, xscale1pmu_init), - XSCALE_PMU_PROBE(ARM_CPU_XSCALE_ARCH_V2, xscale2pmu_init), - { /* sentinel value */ } -}; - -static int xscale_pmu_device_probe(struct platform_device *pdev) -{ - return arm_pmu_device_probe(pdev, NULL, xscale_pmu_probe_table); -} - -static struct platform_driver xscale_pmu_driver = { - .driver = { - .name = "xscale-pmu", - }, - .probe = xscale_pmu_device_probe, -}; - -builtin_platform_driver(xscale_pmu_driver); -#endif /* CONFIG_CPU_XSCALE */ diff --git a/arch/arm/kernel/vmlinux-xip.lds.S b/arch/arm/kernel/vmlinux-xip.lds.S index c16d196b5aad..5eddb75a7174 100644 --- a/arch/arm/kernel/vmlinux-xip.lds.S +++ b/arch/arm/kernel/vmlinux-xip.lds.S @@ -63,7 +63,7 @@ SECTIONS . = ALIGN(4); __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { __start___ex_table = .; - ARM_MMU_KEEP(*(__ex_table)) + ARM_MMU_KEEP(KEEP(*(__ex_table))) __stop___ex_table = .; } @@ -83,7 +83,7 @@ SECTIONS } .init.arch.info : { __arch_info_begin = .; - *(.arch.info.init) + KEEP(*(.arch.info.init)) __arch_info_end = .; } .init.tagtable : { diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S index bd9127c4b451..de373c6c2ae8 100644 --- a/arch/arm/kernel/vmlinux.lds.S +++ b/arch/arm/kernel/vmlinux.lds.S @@ -74,7 +74,7 @@ SECTIONS . = ALIGN(4); __ex_table : AT(ADDR(__ex_table) - LOAD_OFFSET) { __start___ex_table = .; - ARM_MMU_KEEP(*(__ex_table)) + ARM_MMU_KEEP(KEEP(*(__ex_table))) __stop___ex_table = .; } @@ -99,7 +99,7 @@ SECTIONS } .init.arch.info : { __arch_info_begin = .; - *(.arch.info.init) + KEEP(*(.arch.info.init)) __arch_info_end = .; } .init.tagtable : { @@ -116,7 +116,7 @@ SECTIONS #endif .init.pv_table : { __pv_table_begin = .; - *(.pv_table) + KEEP(*(.pv_table)) __pv_table_end = .; } diff --git a/arch/arm/mach-alpine/alpine_cpu_pm.c b/arch/arm/mach-alpine/alpine_cpu_pm.c index 13ae8412e9ce..b48da6f12b6c 100644 --- a/arch/arm/mach-alpine/alpine_cpu_pm.c +++ b/arch/arm/mach-alpine/alpine_cpu_pm.c @@ -29,7 +29,7 @@ int alpine_cpu_wakeup(unsigned int phys_cpu, uint32_t phys_resume_addr) /* * Set CPU resume address - * secure firmware running on boot will jump to this address - * after setting proper CPU mode, and initialiing e.g. secure + * after setting proper CPU mode, and initializing e.g. secure * regs (the same mode all CPUs are booted to - usually HYP) */ writel(phys_resume_addr, diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c index 1e4cd502340e..7695cfce01a1 100644 --- a/arch/arm/mach-pxa/devices.c +++ b/arch/arm/mach-pxa/devices.c @@ -7,6 +7,7 @@ #include <linux/clk-provider.h> #include <linux/dma-mapping.h> #include <linux/dmaengine.h> +#include <linux/gpio-pxa.h> #include <linux/platform_data/i2c-pxa.h> #include <linux/soc/pxa/cpu.h> @@ -17,6 +18,7 @@ #include <linux/platform_data/usb-ohci-pxa27x.h> #include <linux/platform_data/mmp_dma.h> +#include "mfp-pxa2xx.h" #include "regs-ost.h" #include "reset.h" #include "devices.h" @@ -46,7 +48,7 @@ struct platform_device pxa_device_pmu = { .num_resources = 1, }; -static struct resource pxamci_resources[] = { +static const struct resource pxamci_resources[] = { [0] = { .start = 0x41100000, .end = 0x41100fff, @@ -59,22 +61,26 @@ static struct resource pxamci_resources[] = { }, }; -static u64 pxamci_dmamask = 0xffffffffUL; - -struct platform_device pxa_device_mci = { - .name = "pxa2xx-mci", - .id = 0, - .dev = { - .dma_mask = &pxamci_dmamask, - .coherent_dma_mask = 0xffffffff, - }, - .num_resources = ARRAY_SIZE(pxamci_resources), - .resource = pxamci_resources, -}; - -void __init pxa_set_mci_info(struct pxamci_platform_data *info) +void __init pxa_set_mci_info(const struct pxamci_platform_data *info, + const struct property_entry *props) { - pxa_register_device(&pxa_device_mci, info); + const struct platform_device_info mci_info = { + .name = "pxa2xx-mci", + .id = 0, + .res = pxamci_resources, + .num_res = ARRAY_SIZE(pxamci_resources), + .data = info, + .size_data = sizeof(*info), + .dma_mask = 0xffffffffUL, + .properties = props, + }; + struct platform_device *mci_dev; + int err; + + mci_dev = platform_device_register_full(&mci_info); + err = PTR_ERR_OR_ZERO(mci_dev); + if (err) + pr_err("Unable to create mci device: %d\n", err); } static struct pxa2xx_udc_mach_info pxa_udc_info = { @@ -627,6 +633,11 @@ struct platform_device pxa27x_device_pwm1 = { }; #endif /* CONFIG_PXA27x || CONFIG_PXA3xx */ +#if defined(CONFIG_PXA25x) || defined(CONFIG_PXA27x) +const struct software_node pxa2xx_gpiochip_node = { + .name = "gpio-pxa", +}; + struct resource pxa_resource_gpio[] = { { .start = 0x40e00000, @@ -650,11 +661,19 @@ struct resource pxa_resource_gpio[] = { }, }; +static struct pxa_gpio_platform_data pxa2xx_gpio_info = { + .irq_base = PXA_GPIO_TO_IRQ(0), + .gpio_set_wake = gpio_set_wake, +}; + struct platform_device pxa25x_device_gpio = { .name = "pxa25x-gpio", .id = -1, .num_resources = ARRAY_SIZE(pxa_resource_gpio), .resource = pxa_resource_gpio, + .dev = { + .platform_data = &pxa2xx_gpio_info, + }, }; struct platform_device pxa27x_device_gpio = { @@ -662,7 +681,11 @@ struct platform_device pxa27x_device_gpio = { .id = -1, .num_resources = ARRAY_SIZE(pxa_resource_gpio), .resource = pxa_resource_gpio, + .dev = { + .platform_data = &pxa2xx_gpio_info, + }, }; +#endif /* CONFIG_PXA25x || CONFIG_PXA27x */ static struct resource pxa_dma_resource[] = { [0] = { diff --git a/arch/arm/mach-pxa/devices.h b/arch/arm/mach-pxa/devices.h index 82c83939017a..72c556ff67db 100644 --- a/arch/arm/mach-pxa/devices.h +++ b/arch/arm/mach-pxa/devices.h @@ -4,7 +4,6 @@ struct mmp_dma_platdata; extern struct platform_device pxa_device_pmu; -extern struct platform_device pxa_device_mci; extern struct platform_device pxa3xx_device_mci2; extern struct platform_device pxa3xx_device_mci3; extern struct platform_device pxa25x_device_udc; @@ -53,8 +52,8 @@ extern struct platform_device pxa_device_asoc_ssp4; extern struct platform_device pxa25x_device_gpio; extern struct platform_device pxa27x_device_gpio; -extern struct platform_device pxa3xx_device_gpio; -extern struct platform_device pxa93x_device_gpio; + +extern const struct software_node pxa2xx_gpiochip_node; void __init pxa_register_device(struct platform_device *dev, void *data); void __init pxa2xx_set_dmac_info(struct mmp_dma_platdata *dma_pdata); diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c index c9f0f62187bd..1713bdf3b71e 100644 --- a/arch/arm/mach-pxa/gumstix.c +++ b/arch/arm/mach-pxa/gumstix.c @@ -21,6 +21,7 @@ #include <linux/mtd/mtd.h> #include <linux/mtd/partitions.h> #include <linux/gpio/machine.h> +#include <linux/gpio/property.h> #include <linux/gpio.h> #include <linux/err.h> #include <linux/clk.h> @@ -40,6 +41,7 @@ #include <linux/platform_data/mmc-pxamci.h> #include "udc.h" #include "gumstix.h" +#include "devices.h" #include "generic.h" @@ -90,7 +92,7 @@ static struct pxamci_platform_data gumstix_mci_platform_data = { static void __init gumstix_mmc_init(void) { - pxa_set_mci_info(&gumstix_mci_platform_data); + pxa_set_mci_info(&gumstix_mci_platform_data, NULL); } #else static void __init gumstix_mmc_init(void) @@ -99,27 +101,24 @@ static void __init gumstix_mmc_init(void) } #endif -#ifdef CONFIG_USB_PXA25X -static struct gpiod_lookup_table gumstix_gpio_vbus_gpiod_table = { - .dev_id = "gpio-vbus", - .table = { - GPIO_LOOKUP("gpio-pxa", GPIO_GUMSTIX_USB_GPIOn, - "vbus", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("gpio-pxa", GPIO_GUMSTIX_USB_GPIOx, - "pullup", GPIO_ACTIVE_HIGH), - { }, - }, +#if IS_ENABLED(CONFIG_USB_PXA25X) +static const struct property_entry gumstix_vbus_props[] __initconst = { + PROPERTY_ENTRY_GPIO("vbus-gpios", &pxa2xx_gpiochip_node, + GPIO_GUMSTIX_USB_GPIOn, GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("pullup-gpios", &pxa2xx_gpiochip_node, + GPIO_GUMSTIX_USB_GPIOx, GPIO_ACTIVE_HIGH), + { } }; -static struct platform_device gumstix_gpio_vbus = { - .name = "gpio-vbus", - .id = -1, +static const struct platform_device_info gumstix_gpio_vbus_info __initconst = { + .name = "gpio-vbus", + .id = PLATFORM_DEVID_NONE, + .properties = gumstix_vbus_props, }; static void __init gumstix_udc_init(void) { - gpiod_add_lookup_table(&gumstix_gpio_vbus_gpiod_table); - platform_device_register(&gumstix_gpio_vbus); + platform_device_register_full(&gumstix_gpio_vbus_info); } #else static void gumstix_udc_init(void) diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index 02712d24be82..03e34841fc00 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c @@ -178,12 +178,8 @@ void __init pxa25x_map_io(void) pxa25x_get_clk_frequency_khz(1); } -static struct pxa_gpio_platform_data pxa25x_gpio_info __initdata = { - .irq_base = PXA_GPIO_TO_IRQ(0), - .gpio_set_wake = gpio_set_wake, -}; - static struct platform_device *pxa25x_devices[] __initdata = { + &pxa25x_device_gpio, &pxa25x_device_udc, &pxa_device_pmu, &pxa_device_i2s, @@ -243,8 +239,8 @@ static int __init pxa25x_init(void) register_syscore_ops(&pxa2xx_mfp_syscore_ops); if (!of_have_populated_dt()) { + software_node_register(&pxa2xx_gpiochip_node); pxa2xx_set_dmac_info(&pxa25x_dma_pdata); - pxa_register_device(&pxa25x_device_gpio, &pxa25x_gpio_info); ret = platform_add_devices(pxa25x_devices, ARRAY_SIZE(pxa25x_devices)); } diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index d71491e2e1d6..f8382477d629 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c @@ -276,12 +276,8 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info) pxa_register_device(&pxa27x_device_i2c_power, info); } -static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = { - .irq_base = PXA_GPIO_TO_IRQ(0), - .gpio_set_wake = gpio_set_wake, -}; - static struct platform_device *devices[] __initdata = { + &pxa27x_device_gpio, &pxa27x_device_udc, &pxa_device_pmu, &pxa_device_i2s, @@ -345,8 +341,7 @@ static int __init pxa27x_init(void) register_syscore_ops(&pxa2xx_mfp_syscore_ops); if (!of_have_populated_dt()) { - pxa_register_device(&pxa27x_device_gpio, - &pxa27x_gpio_info); + software_node_register(&pxa2xx_gpiochip_node); pxa2xx_set_dmac_info(&pxa27x_dma_pdata); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); diff --git a/arch/arm/mach-pxa/spitz.c b/arch/arm/mach-pxa/spitz.c index 10ab16dcd827..452bf7aac1fa 100644 --- a/arch/arm/mach-pxa/spitz.c +++ b/arch/arm/mach-pxa/spitz.c @@ -14,6 +14,7 @@ #include <linux/gpio_keys.h> #include <linux/gpio.h> #include <linux/gpio/machine.h> +#include <linux/gpio/property.h> #include <linux/leds.h> #include <linux/i2c.h> #include <linux/platform_data/i2c-pxa.h> @@ -28,6 +29,7 @@ #include <linux/input/matrix_keypad.h> #include <linux/regulator/machine.h> #include <linux/io.h> +#include <linux/property.h> #include <linux/reboot.h> #include <linux/memblock.h> @@ -128,6 +130,19 @@ static unsigned long spitz_pin_config[] __initdata = { GPIO1_GPIO | WAKEUP_ON_EDGE_FALL, /* SPITZ_GPIO_RESET */ }; +static const struct software_node spitz_scoop_1_gpiochip_node = { + .name = "sharp-scoop.0", +}; + +/* Only on Spitz */ +static const struct software_node spitz_scoop_2_gpiochip_node = { + .name = "sharp-scoop.1", +}; + +/* Only on Akita */ +static const struct software_node akita_max7310_gpiochip_node = { + .name = "i2c-max7310", +}; /****************************************************************************** * Scoop GPIO expander @@ -452,35 +467,64 @@ static inline void spitz_keys_init(void) {} * LEDs ******************************************************************************/ #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) -static struct gpio_led spitz_gpio_leds[] = { - { - .name = "spitz:amber:charge", - .default_trigger = "sharpsl-charge", - .gpio = SPITZ_GPIO_LED_ORANGE, - }, - { - .name = "spitz:green:hddactivity", - .default_trigger = "disk-activity", - .gpio = SPITZ_GPIO_LED_GREEN, - }, +static const struct software_node spitz_gpio_leds_node = { + .name = "spitz-leds", }; -static struct gpio_led_platform_data spitz_gpio_leds_info = { - .leds = spitz_gpio_leds, - .num_leds = ARRAY_SIZE(spitz_gpio_leds), +static const struct property_entry spitz_orange_led_props[] = { + PROPERTY_ENTRY_STRING("linux,default-trigger", "sharpsl-charge"), + PROPERTY_ENTRY_GPIO("gpios", + &spitz_scoop_1_gpiochip_node, 6, GPIO_ACTIVE_HIGH), + { } }; -static struct platform_device spitz_led_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &spitz_gpio_leds_info, - }, +static const struct software_node spitz_orange_led_node = { + .name = "spitz:amber:charge", + .parent = &spitz_gpio_leds_node, + .properties = spitz_orange_led_props, +}; + +static const struct property_entry spitz_green_led_props[] = { + PROPERTY_ENTRY_STRING("linux,default-trigger", "disk-activity"), + PROPERTY_ENTRY_GPIO("gpios", + &spitz_scoop_1_gpiochip_node, 0, GPIO_ACTIVE_HIGH), + { } +}; + +static const struct software_node spitz_green_led_node = { + .name = "spitz:green:hddactivity", + .parent = &spitz_gpio_leds_node, + .properties = spitz_green_led_props, +}; + +static const struct software_node *spitz_gpio_leds_swnodes[] = { + &spitz_gpio_leds_node, + &spitz_orange_led_node, + &spitz_green_led_node, + NULL }; static void __init spitz_leds_init(void) { - platform_device_register(&spitz_led_device); + struct platform_device_info led_info = { + .name = "leds-gpio", + .id = PLATFORM_DEVID_NONE, + }; + struct platform_device *led_dev; + int err; + + err = software_node_register_node_group(spitz_gpio_leds_swnodes); + if (err) { + pr_err("failed to register LED software nodes: %d\n", err); + return; + } + + led_info.fwnode = software_node_fwnode(&spitz_gpio_leds_node); + + led_dev = platform_device_register_full(&led_info); + err = PTR_ERR_OR_ZERO(led_dev); + if (err) + pr_err("failed to create LED device: %d\n", err); } #else static inline void spitz_leds_init(void) {} @@ -490,49 +534,43 @@ static inline void spitz_leds_init(void) {} * SSP Devices ******************************************************************************/ #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MODULE) -static void spitz_ads7846_wait_for_hsync(void) -{ - while (gpio_get_value(SPITZ_GPIO_HSYNC)) - cpu_relax(); - while (!gpio_get_value(SPITZ_GPIO_HSYNC)) - cpu_relax(); -} +static const struct property_entry spitz_ads7846_props[] = { + PROPERTY_ENTRY_STRING("compatible", "ti,ads7846"), + PROPERTY_ENTRY_U32("touchscreen-max-pressure", 1024), + PROPERTY_ENTRY_U16("ti,x-plate-ohms", 419), + PROPERTY_ENTRY_U16("ti,y-plate-ohms", 486), + PROPERTY_ENTRY_U16("ti,vref-delay-usecs", 100), + PROPERTY_ENTRY_GPIO("pendown-gpios", &pxa2xx_gpiochip_node, + SPITZ_GPIO_TP_INT, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_GPIO("ti,hsync-gpios", &pxa2xx_gpiochip_node, + SPITZ_GPIO_HSYNC, GPIO_ACTIVE_LOW), + { } +}; -static struct ads7846_platform_data spitz_ads7846_info = { - .model = 7846, - .vref_delay_usecs = 100, - .x_plate_ohms = 419, - .y_plate_ohms = 486, - .pressure_max = 1024, - .wait_for_sync = spitz_ads7846_wait_for_hsync, +static const struct software_node spitz_ads7846_swnode = { + .name = "ads7846", + .properties = spitz_ads7846_props, }; -static struct gpiod_lookup_table spitz_ads7846_gpio_table = { - .dev_id = "spi2.0", - .table = { - GPIO_LOOKUP("gpio-pxa", SPITZ_GPIO_TP_INT, - "pendown", GPIO_ACTIVE_LOW), - { } - }, +static const struct property_entry spitz_lcdcon_props[] = { + PROPERTY_ENTRY_GPIO("BL_CONT-gpios", + &spitz_scoop_2_gpiochip_node, 6, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_GPIO("BL_ON-gpios", + &spitz_scoop_2_gpiochip_node, 7, GPIO_ACTIVE_HIGH), + { } }; -static struct gpiod_lookup_table spitz_lcdcon_gpio_table = { - .dev_id = "spi2.1", - .table = { - GPIO_LOOKUP("sharp-scoop.1", 6, "BL_CONT", GPIO_ACTIVE_LOW), - GPIO_LOOKUP("sharp-scoop.1", 7, "BL_ON", GPIO_ACTIVE_HIGH), - { }, - }, +static const struct property_entry akita_lcdcon_props[] = { + PROPERTY_ENTRY_GPIO("BL_ON-gpios", + &akita_max7310_gpiochip_node, 3, GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("BL_CONT-gpios", + &akita_max7310_gpiochip_node, 4, GPIO_ACTIVE_LOW), + { } }; -static struct gpiod_lookup_table akita_lcdcon_gpio_table = { - .dev_id = "spi2.1", - .table = { - GPIO_LOOKUP("i2c-max7310", 3, "BL_ON", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("i2c-max7310", 4, "BL_CONT", GPIO_ACTIVE_LOW), - { }, - }, +static struct software_node spitz_lcdcon_node = { + .name = "spitz-lcdcon", }; static struct corgi_lcd_platform_data spitz_lcdcon_info = { @@ -549,7 +587,7 @@ static struct spi_board_info spitz_spi_devices[] = { .max_speed_hz = 1200000, .bus_num = 2, .chip_select = 0, - .platform_data = &spitz_ads7846_info, + .swnode = &spitz_ads7846_swnode, .irq = PXA_GPIO_TO_IRQ(SPITZ_GPIO_TP_INT), }, { .modalias = "corgi-lcd", @@ -557,6 +595,7 @@ static struct spi_board_info spitz_spi_devices[] = { .bus_num = 2, .chip_select = 1, .platform_data = &spitz_lcdcon_info, + .swnode = &spitz_lcdcon_node, }, { .modalias = "max1111", .max_speed_hz = 450000, @@ -565,53 +604,40 @@ static struct spi_board_info spitz_spi_devices[] = { }, }; -static struct gpiod_lookup_table spitz_spi_gpio_table = { - .dev_id = "spi2", - .table = { - GPIO_LOOKUP_IDX("gpio-pxa", SPITZ_GPIO_ADS7846_CS, "cs", 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("gpio-pxa", SPITZ_GPIO_LCDCON_CS, "cs", 1, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("gpio-pxa", SPITZ_GPIO_MAX1111_CS, "cs", 2, GPIO_ACTIVE_LOW), - { }, - }, +static const struct software_node_ref_args spitz_spi_gpio_refs[] = { + SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_ADS7846_CS, + GPIO_ACTIVE_LOW), + SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_LCDCON_CS, + GPIO_ACTIVE_LOW), + SOFTWARE_NODE_REFERENCE(&pxa2xx_gpiochip_node, SPITZ_GPIO_MAX1111_CS, + GPIO_ACTIVE_LOW), }; static const struct property_entry spitz_spi_properties[] = { - PROPERTY_ENTRY_U32("num-cs", 3), + PROPERTY_ENTRY_REF_ARRAY("gpios", spitz_spi_gpio_refs), { } }; -static const struct software_node spitz_spi_node = { +static const struct platform_device_info spitz_spi_device_info = { + .name = "pxa2xx-spi", + /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1 */ + .id = 2, .properties = spitz_spi_properties, }; static void __init spitz_spi_init(void) { struct platform_device *pd; - int id = 2; int err; - if (machine_is_akita()) - gpiod_add_lookup_table(&akita_lcdcon_gpio_table); - else - gpiod_add_lookup_table(&spitz_lcdcon_gpio_table); - - gpiod_add_lookup_table(&spitz_ads7846_gpio_table); - gpiod_add_lookup_table(&spitz_spi_gpio_table); - - /* pxa2xx-spi platform-device ID equals respective SSP platform-device ID + 1 */ - pd = platform_device_alloc("pxa2xx-spi", id); - if (pd == NULL) { - pr_err("pxa2xx-spi: failed to allocate device id %d\n", id); - } else { - err = device_add_software_node(&pd->dev, &spitz_spi_node); - if (err) { - platform_device_put(pd); - pr_err("pxa2xx-spi: failed to add software node\n"); - } else { - platform_device_add(pd); - } - } + pd = platform_device_register_full(&spitz_spi_device_info); + err = PTR_ERR_OR_ZERO(pd); + if (err) + pr_err("pxa2xx-spi: failed to instantiate SPI controller: %d\n", + err); + spitz_lcdcon_node.properties = machine_is_akita() ? + akita_lcdcon_props : spitz_lcdcon_props; spi_register_board_info(ARRAY_AND_SIZE(spitz_spi_devices)); } #else @@ -644,21 +670,17 @@ static struct pxamci_platform_data spitz_mci_platform_data = { .setpower = spitz_mci_setpower, }; -static struct gpiod_lookup_table spitz_mci_gpio_table = { - .dev_id = "pxa2xx-mci.0", - .table = { - GPIO_LOOKUP("gpio-pxa", SPITZ_GPIO_nSD_DETECT, - "cd", GPIO_ACTIVE_LOW), - GPIO_LOOKUP("gpio-pxa", SPITZ_GPIO_nSD_WP, - "wp", GPIO_ACTIVE_LOW), - { }, - }, +static const struct property_entry spitz_mci_props[] __initconst = { + PROPERTY_ENTRY_GPIO("cd-gpios", &pxa2xx_gpiochip_node, + SPITZ_GPIO_nSD_DETECT, GPIO_ACTIVE_LOW), + PROPERTY_ENTRY_GPIO("wp-gpios", &pxa2xx_gpiochip_node, + SPITZ_GPIO_nSD_WP, GPIO_ACTIVE_LOW), + { } }; static void __init spitz_mmc_init(void) { - gpiod_add_lookup_table(&spitz_mci_gpio_table); - pxa_set_mci_info(&spitz_mci_platform_data); + pxa_set_mci_info(&spitz_mci_platform_data, spitz_mci_props); } #else static inline void spitz_mmc_init(void) {} @@ -957,24 +979,24 @@ static void __init spitz_i2c_init(void) static inline void spitz_i2c_init(void) {} #endif -static struct gpiod_lookup_table spitz_audio_gpio_table = { - .dev_id = "spitz-audio", - .table = { - GPIO_LOOKUP("sharp-scoop.0", 3, "mute-l", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("sharp-scoop.0", 4, "mute-r", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("sharp-scoop.1", 8, "mic", GPIO_ACTIVE_HIGH), - { }, - }, +static const struct property_entry spitz_audio_props[] = { + PROPERTY_ENTRY_GPIO("mute-l-gpios", &spitz_scoop_1_gpiochip_node, 3, + GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("mute-r-gpios", &spitz_scoop_1_gpiochip_node, 4, + GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("mic-gpios", &spitz_scoop_2_gpiochip_node, 8, + GPIO_ACTIVE_HIGH), + { } }; -static struct gpiod_lookup_table akita_audio_gpio_table = { - .dev_id = "spitz-audio", - .table = { - GPIO_LOOKUP("sharp-scoop.0", 3, "mute-l", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("sharp-scoop.0", 4, "mute-r", GPIO_ACTIVE_HIGH), - GPIO_LOOKUP("i2c-max7310", 2, "mic", GPIO_ACTIVE_HIGH), - { }, - }, +static const struct property_entry akita_audio_props[] = { + PROPERTY_ENTRY_GPIO("mute-l-gpios", &spitz_scoop_1_gpiochip_node, 3, + GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("mute-r-gpios", &spitz_scoop_1_gpiochip_node, 4, + GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("mic-gpios", &akita_max7310_gpiochip_node, 2, + GPIO_ACTIVE_HIGH), + { } }; /****************************************************************************** @@ -982,12 +1004,14 @@ static struct gpiod_lookup_table akita_audio_gpio_table = { ******************************************************************************/ static inline void spitz_audio_init(void) { - if (machine_is_akita()) - gpiod_add_lookup_table(&akita_audio_gpio_table); - else - gpiod_add_lookup_table(&spitz_audio_gpio_table); - - platform_device_register_simple("spitz-audio", -1, NULL, 0); + struct platform_device_info audio_info = { + .name = "spitz-audio", + .id = PLATFORM_DEVID_NONE, + .properties = machine_is_akita() ? + akita_audio_props : spitz_audio_props, + }; + + platform_device_register_full(&audio_info); } /****************************************************************************** @@ -1010,6 +1034,12 @@ static void spitz_restart(enum reboot_mode mode, const char *cmd) static void __init spitz_init(void) { + software_node_register(&spitz_scoop_1_gpiochip_node); + if (machine_is_akita()) + software_node_register(&akita_max7310_gpiochip_node); + else + software_node_register(&spitz_scoop_2_gpiochip_node); + init_gpio_reset(SPITZ_GPIO_ON_RESET, 1, 0); pm_power_off = spitz_poweroff; diff --git a/arch/arm/mach-rpc/ecard.c b/arch/arm/mach-rpc/ecard.c index c30df1097c52..9f7454b8efa7 100644 --- a/arch/arm/mach-rpc/ecard.c +++ b/arch/arm/mach-rpc/ecard.c @@ -1109,7 +1109,7 @@ void ecard_remove_driver(struct ecard_driver *drv) driver_unregister(&drv->drv); } -static int ecard_match(struct device *_dev, struct device_driver *_drv) +static int ecard_match(struct device *_dev, const struct device_driver *_drv) { struct expansion_card *ec = ECARD_DEV(_dev); struct ecard_driver *drv = ECARD_DRV(_drv); diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig index ae21a9f78f9c..630b992f32b1 100644 --- a/arch/arm/mach-stm32/Kconfig +++ b/arch/arm/mach-stm32/Kconfig @@ -11,7 +11,7 @@ menuconfig ARCH_STM32 select CLKSRC_STM32 select PINCTRL select RESET_CONTROLLER - select STM32_EXTI + select STM32_EXTI if ARM_SINGLE_ARMV7M select STM32_FIREWALL help Support for STMicroelectronics STM32 processors. diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 18d37f90cdfe..3ec810b6f1a7 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c @@ -8,35 +8,49 @@ * Copyright (C) 2010 Google, Inc. */ -#include <linux/property.h> +#include <linux/err.h> #include <linux/gpio/machine.h> +#include <linux/gpio/property.h> #include <linux/platform_device.h> +#include <linux/printk.h> +#include <linux/property.h> #include "board.h" -static struct property_entry wifi_rfkill_prop[] __initdata = { - PROPERTY_ENTRY_STRING("name", "wifi_rfkill"), - PROPERTY_ENTRY_STRING("type", "wlan"), - { }, +static const struct software_node tegra_gpiochip_node = { + .name = "tegra-gpio", }; -static struct platform_device wifi_rfkill_device = { - .name = "rfkill_gpio", - .id = -1, +static const struct property_entry wifi_rfkill_prop[] __initconst = { + PROPERTY_ENTRY_STRING("name", "wifi_rfkill"), + PROPERTY_ENTRY_STRING("type", "wlan"), + PROPERTY_ENTRY_GPIO("reset-gpios", + &tegra_gpiochip_node, 25, GPIO_ACTIVE_HIGH), + PROPERTY_ENTRY_GPIO("shutdown-gpios", + &tegra_gpiochip_node, 85, GPIO_ACTIVE_HIGH), + { } }; -static struct gpiod_lookup_table wifi_gpio_lookup = { - .dev_id = "rfkill_gpio", - .table = { - GPIO_LOOKUP("tegra-gpio", 25, "reset", 0), - GPIO_LOOKUP("tegra-gpio", 85, "shutdown", 0), - { }, - }, +static const struct platform_device_info wifi_rfkill_info __initconst = { + .name = "rfkill_gpio", + .id = PLATFORM_DEVID_NONE, + .properties = wifi_rfkill_prop, }; void __init tegra_paz00_wifikill_init(void) { - device_create_managed_software_node(&wifi_rfkill_device.dev, wifi_rfkill_prop, NULL); - gpiod_add_lookup_table(&wifi_gpio_lookup); - platform_device_register(&wifi_rfkill_device); + struct platform_device *pd; + int err; + + err = software_node_register(&tegra_gpiochip_node); + if (err) { + pr_err("failed to register %s node: %d\n", + tegra_gpiochip_node.name, err); + return; + } + + pd = platform_device_register_full(&wifi_rfkill_info); + err = PTR_ERR_OR_ZERO(pd); + if (err) + pr_err("failed to register WiFi rfkill device: %d\n", err); } diff --git a/arch/arm/mach-versatile/Kconfig b/arch/arm/mach-versatile/Kconfig index e029270c2687..513618078440 100644 --- a/arch/arm/mach-versatile/Kconfig +++ b/arch/arm/mach-versatile/Kconfig @@ -278,15 +278,6 @@ config ARCH_VEXPRESS_CORTEX_A5_A9_ERRATA build a working kernel, you must also enable relevant core tile support or Flattened Device Tree based support options. -config ARCH_VEXPRESS_DCSCB - bool "Dual Cluster System Control Block (DCSCB) support" - depends on MCPM - select ARM_CCI400_PORT_CTRL - help - Support for the Dual Cluster System Configuration Block (DCSCB). - This is needed to provide CPU and cluster power management - on RTSM implementing big.LITTLE. - config ARCH_VEXPRESS_SPC bool "Versatile Express Serial Power Controller (SPC)" select PM_OPP diff --git a/arch/arm/mach-versatile/Makefile b/arch/arm/mach-versatile/Makefile index 27d712bcf1af..d819fb2fc450 100644 --- a/arch/arm/mach-versatile/Makefile +++ b/arch/arm/mach-versatile/Makefile @@ -16,9 +16,6 @@ obj-$(CONFIG_ARCH_REALVIEW) += realview.o # vexpress obj-$(CONFIG_ARCH_VEXPRESS) := v2m.o -obj-$(CONFIG_ARCH_VEXPRESS_DCSCB) += dcscb.o dcscb_setup.o -CFLAGS_dcscb.o += -march=armv7-a -CFLAGS_REMOVE_dcscb.o = -pg obj-$(CONFIG_ARCH_VEXPRESS_SPC) += spc.o CFLAGS_REMOVE_spc.o = -pg obj-$(CONFIG_ARCH_VEXPRESS_TC2_PM) += tc2_pm.o diff --git a/arch/arm/mach-versatile/dcscb.c b/arch/arm/mach-versatile/dcscb.c deleted file mode 100644 index d8797350996d..000000000000 --- a/arch/arm/mach-versatile/dcscb.c +++ /dev/null @@ -1,173 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * dcscb.c - Dual Cluster System Configuration Block - * - * Created by: Nicolas Pitre, May 2012 - * Copyright: (C) 2012-2013 Linaro Limited - */ - -#include <linux/init.h> -#include <linux/kernel.h> -#include <linux/io.h> -#include <linux/errno.h> -#include <linux/of_address.h> -#include <linux/vexpress.h> -#include <linux/arm-cci.h> - -#include <asm/mcpm.h> -#include <asm/proc-fns.h> -#include <asm/cacheflush.h> -#include <asm/cputype.h> -#include <asm/cp15.h> - -#include "vexpress.h" - -#define RST_HOLD0 0x0 -#define RST_HOLD1 0x4 -#define SYS_SWRESET 0x8 -#define RST_STAT0 0xc -#define RST_STAT1 0x10 -#define EAG_CFG_R 0x20 -#define EAG_CFG_W 0x24 -#define KFC_CFG_R 0x28 -#define KFC_CFG_W 0x2c -#define DCS_CFG_R 0x30 - -static void __iomem *dcscb_base; -static int dcscb_allcpus_mask[2]; - -static int dcscb_cpu_powerup(unsigned int cpu, unsigned int cluster) -{ - unsigned int rst_hold, cpumask = (1 << cpu); - - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - if (cluster >= 2 || !(cpumask & dcscb_allcpus_mask[cluster])) - return -EINVAL; - - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); - rst_hold &= ~(cpumask | (cpumask << 4)); - writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); - return 0; -} - -static int dcscb_cluster_powerup(unsigned int cluster) -{ - unsigned int rst_hold; - - pr_debug("%s: cluster %u\n", __func__, cluster); - if (cluster >= 2) - return -EINVAL; - - /* remove cluster reset and add individual CPU's reset */ - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); - rst_hold &= ~(1 << 8); - rst_hold |= dcscb_allcpus_mask[cluster]; - writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); - return 0; -} - -static void dcscb_cpu_powerdown_prepare(unsigned int cpu, unsigned int cluster) -{ - unsigned int rst_hold; - - pr_debug("%s: cpu %u cluster %u\n", __func__, cpu, cluster); - BUG_ON(cluster >= 2 || !((1 << cpu) & dcscb_allcpus_mask[cluster])); - - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); - rst_hold |= (1 << cpu); - writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); -} - -static void dcscb_cluster_powerdown_prepare(unsigned int cluster) -{ - unsigned int rst_hold; - - pr_debug("%s: cluster %u\n", __func__, cluster); - BUG_ON(cluster >= 2); - - rst_hold = readl_relaxed(dcscb_base + RST_HOLD0 + cluster * 4); - rst_hold |= (1 << 8); - writel_relaxed(rst_hold, dcscb_base + RST_HOLD0 + cluster * 4); -} - -static void dcscb_cpu_cache_disable(void) -{ - /* Disable and flush the local CPU cache. */ - v7_exit_coherency_flush(louis); -} - -static void dcscb_cluster_cache_disable(void) -{ - /* Flush all cache levels for this cluster. */ - v7_exit_coherency_flush(all); - - /* - * A full outer cache flush could be needed at this point - * on platforms with such a cache, depending on where the - * outer cache sits. In some cases the notion of a "last - * cluster standing" would need to be implemented if the - * outer cache is shared across clusters. In any case, when - * the outer cache needs flushing, there is no concurrent - * access to the cache controller to worry about and no - * special locking besides what is already provided by the - * MCPM state machinery is needed. - */ - - /* - * Disable cluster-level coherency by masking - * incoming snoops and DVM messages: - */ - cci_disable_port_by_cpu(read_cpuid_mpidr()); -} - -static const struct mcpm_platform_ops dcscb_power_ops = { - .cpu_powerup = dcscb_cpu_powerup, - .cluster_powerup = dcscb_cluster_powerup, - .cpu_powerdown_prepare = dcscb_cpu_powerdown_prepare, - .cluster_powerdown_prepare = dcscb_cluster_powerdown_prepare, - .cpu_cache_disable = dcscb_cpu_cache_disable, - .cluster_cache_disable = dcscb_cluster_cache_disable, -}; - -extern void dcscb_power_up_setup(unsigned int affinity_level); - -static int __init dcscb_init(void) -{ - struct device_node *node; - unsigned int cfg; - int ret; - - if (!cci_probed()) - return -ENODEV; - - node = of_find_compatible_node(NULL, NULL, "arm,rtsm,dcscb"); - if (!node) - return -ENODEV; - dcscb_base = of_iomap(node, 0); - of_node_put(node); - if (!dcscb_base) - return -EADDRNOTAVAIL; - cfg = readl_relaxed(dcscb_base + DCS_CFG_R); - dcscb_allcpus_mask[0] = (1 << (((cfg >> 16) >> (0 << 2)) & 0xf)) - 1; - dcscb_allcpus_mask[1] = (1 << (((cfg >> 16) >> (1 << 2)) & 0xf)) - 1; - - ret = mcpm_platform_register(&dcscb_power_ops); - if (!ret) - ret = mcpm_sync_init(dcscb_power_up_setup); - if (ret) { - iounmap(dcscb_base); - return ret; - } - - pr_info("VExpress DCSCB support installed\n"); - - /* - * Future entries into the kernel can now go - * through the cluster entry vectors. - */ - vexpress_flags_set(__pa_symbol(mcpm_entry_point)); - - return 0; -} - -early_initcall(dcscb_init); diff --git a/arch/arm/mach-versatile/dcscb_setup.S b/arch/arm/mach-versatile/dcscb_setup.S deleted file mode 100644 index 92d1fd9d7f6a..000000000000 --- a/arch/arm/mach-versatile/dcscb_setup.S +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Created by: Dave Martin, 2012-06-22 - * Copyright: (C) 2012-2013 Linaro Limited - */ - -#include <linux/linkage.h> - - -ENTRY(dcscb_power_up_setup) - - cmp r0, #0 @ check affinity level - beq 2f - -/* - * Enable cluster-level coherency, in preparation for turning on the MMU. - * The ACTLR SMP bit does not need to be set here, because cpu_resume() - * already restores that. - * - * A15/A7 may not require explicit L2 invalidation on reset, dependent - * on hardware integration decisions. - * For now, this code assumes that L2 is either already invalidated, - * or invalidation is not required. - */ - - b cci_enable_port_for_self - -2: @ Implementation-specific local CPU setup operations should go here, - @ if any. In this case, there is nothing to do. - - bx lr - -ENDPROC(dcscb_power_up_setup) diff --git a/arch/arm/tools/syscall.tbl b/arch/arm/tools/syscall.tbl index 2ed7d229c8f9..23c98203c40f 100644 --- a/arch/arm/tools/syscall.tbl +++ b/arch/arm/tools/syscall.tbl @@ -1,3 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note # # Linux system call numbers and entry vectors # diff --git a/arch/arm/xen/p2m.c b/arch/arm/xen/p2m.c index 309648c17f48..9da57a5b81c7 100644 --- a/arch/arm/xen/p2m.c +++ b/arch/arm/xen/p2m.c @@ -109,7 +109,7 @@ int set_foreign_p2m_mapping(struct gnttab_map_grant_ref *map_ops, * immediate unmapping. */ map_ops[i].status = GNTST_general_error; - unmap.host_addr = map_ops[i].host_addr, + unmap.host_addr = map_ops[i].host_addr; unmap.handle = map_ops[i].handle; map_ops[i].handle = INVALID_GRANT_HANDLE; if (map_ops[i].flags & GNTMAP_device_map) |