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authorGrazvydas Ignotas <notasas@gmail.com>2012-05-06 03:56:52 +0400
committerTony Lindgren <tony@atomide.com>2012-05-09 21:35:48 +0400
commitd723c17ab6e7f04f49cd715d5de4d4f6edf7b28a (patch)
tree87cc4b898126226aa243868a106e323bbaa6ef95 /arch/arm
parent33ee0db53994a574b76e0261fc9a3daf71f4b0d7 (diff)
downloadlinux-d723c17ab6e7f04f49cd715d5de4d4f6edf7b28a.tar.xz
ARM: OMAP2+: remove incorrect irq_chip ack field
Each irq_chip for the main interrupt controller has offsets set for irq masking registers, which added to respective base results in a pointer to appropriate hardware register. However this is not correct for INTC_CONTROL as there is only one INTC_CONTROL register. This does not cause problems because generic ack code is never called, but remove this assignment to avoid confusion. Signed-off-by: Grazvydas Ignotas <notasas@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/mach-omap2/irq.c1
1 files changed, 0 insertions, 1 deletions
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 65f0d2571c9a..c11e8a84c947 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -149,7 +149,6 @@ omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
ct->chip.irq_mask = irq_gc_mask_disable_reg;
ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
- ct->regs.ack = INTC_CONTROL;
ct->regs.enable = INTC_MIR_CLEAR0;
ct->regs.disable = INTC_MIR_SET0;
irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,