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authorRafael J. Wysocki <rafael.j.wysocki@intel.com>2022-03-22 14:15:47 +0300
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2022-03-22 14:15:47 +0300
commit2353828f3695ecbbc3fb4b695fa6c77323db42d0 (patch)
tree6b499f0a770d4cd18a2d3217cf4f9d2cf84f43d5 /arch/arm
parent02b82b02c34321dde10d003aafcd831a769b2a8a (diff)
parentb7f2b0d3511a6bbf9387f08f370f9125663e18d8 (diff)
downloadlinux-2353828f3695ecbbc3fb4b695fa6c77323db42d0.tar.xz
Merge branch 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm
Pull ARM cpufreq updates for 5.18-rc1 fron Viresh Kumar: "- Add per core DVFS support for QCom SoC (Bjorn Andersson), convert to yaml binding (Manivannan Sadhasivam) and various other fixes to the QCom drivers (Luca Weiss). - Add OPP table for imx7s SoC (Denys Drozdov) and minor fixes (Stefan Agner). - Fix CPPC driver's freq/performance conversions (Pierre Gondois). - Minor generic cleanups (Yury Norov)." * 'cpufreq/arm/linux-next' of git://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm: dt-bindings: cpufreq: cpufreq-qcom-hw: Convert to YAML bindings dt-bindings: dvfs: Use MediaTek CPUFREQ HW as an example cpufreq: blocklist Qualcomm sc8280xp and sa8540p in cpufreq-dt-platdev cpufreq: qcom-hw: Add support for per-core-dcvs cpufreq: CPPC: Fix performance/frequency conversion cpufreq: Add i.MX7S to cpufreq-dt-platdev blocklist ARM: dts: imx7s: Define operating points table for cpufreq cpufreq: qcom-cpufreq-nvmem: fix reading of PVS Valid fuse cpufreq: replace cpumask_weight with cpumask_empty where appropriate
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/imx7s.dtsi16
1 files changed, 16 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 52a9aeecdbb2..5af6d58666f4 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -76,6 +76,22 @@
clock-latency = <61036>; /* two CLK32 periods */
clocks = <&clks IMX7D_CLK_ARM>;
cpu-idle-states = <&cpu_sleep_wait>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ #cooling-cells = <2>;
+ nvmem-cells = <&fuse_grade>;
+ nvmem-cell-names = "speed_grade";
+ };
+ };
+
+ cpu0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-792000000 {
+ opp-hz = /bits/ 64 <792000000>;
+ opp-microvolt = <1000000>;
+ clock-latency-ns = <150000>;
+ opp-supported-hw = <0xf>, <0xf>;
};
};