summaryrefslogtreecommitdiff
path: root/arch/arm
diff options
context:
space:
mode:
authorMarek Szyprowski <m.szyprowski@samsung.com>2019-12-11 17:52:17 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2020-02-06 00:22:42 +0300
commitb5cbe8ad1b604c8c3b5a92b7dec14d2c8de2b856 (patch)
tree8288f58397e9327c007231d57f0a635a70546a97 /arch/arm
parente8b0d16e4c7f0e27a5dcee512c7b94b9e43cd506 (diff)
downloadlinux-b5cbe8ad1b604c8c3b5a92b7dec14d2c8de2b856.tar.xz
ARM: dts: sun8i: a83t: Correct USB3503 GPIOs polarity
[ Upstream commit 1c226017d3ec93547b58082bdf778d9db7401c95 ] Current USB3503 driver ignores GPIO polarity and always operates as if the GPIO lines were flagged as ACTIVE_HIGH. Fix the polarity for the existing USB3503 chip applications to match the chip specification and common convention for naming the pins. The only pin, which has to be ACTIVE_LOW is the reset pin. The remaining are ACTIVE_HIGH. This change allows later to fix the USB3503 driver to properly use generic GPIO bindings and read polarity from DT. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
index fb928503ad45..d9be511f054f 100644
--- a/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-cubietruck-plus.dts
@@ -101,7 +101,7 @@
initial-mode = <1>; /* initialize in HUB mode */
disabled-ports = <1>;
intn-gpios = <&pio 7 5 GPIO_ACTIVE_HIGH>; /* PH5 */
- reset-gpios = <&pio 4 16 GPIO_ACTIVE_HIGH>; /* PE16 */
+ reset-gpios = <&pio 4 16 GPIO_ACTIVE_LOW>; /* PE16 */
connect-gpios = <&pio 4 17 GPIO_ACTIVE_HIGH>; /* PE17 */
refclk-frequency = <19200000>;
};