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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2019-09-27 21:09:21 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2020-02-24 10:36:39 +0300 |
| commit | f9b42cb09d8ba6f480b0ae9e21ac7b2ed54db58d (patch) | |
| tree | ba5b707ddd31534af696c327a22253f0a586639e /arch/arm | |
| parent | d80f9dfe47ce542eda62eac5ca67992b28c000e8 (diff) | |
| download | linux-f9b42cb09d8ba6f480b0ae9e21ac7b2ed54db58d.tar.xz | |
clk: renesas: rcar-gen3: Allow changing the RPC[D2] clocks
[ Upstream commit 0d67c0340a60829c5c1b7d09629d23bbd67696f3 ]
I was unable to get clk_set_rate() setting a lower RPC-IF clock frequency
and that issue boiled down to me not passing CLK_SET_RATE_PARENT flag to
clk_register_composite() when registering the RPC[D2] clocks...
Fixes: db4a0073cc82 ("clk: renesas: rcar-gen3: Add RPC clocks")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Link: https://lore.kernel.org/r/be27a344-d8bf-9e0c-8950-2d1b48498496@cogentembedded.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Diffstat (limited to 'arch/arm')
0 files changed, 0 insertions, 0 deletions