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| author | Marc Zyngier <maz@kernel.org> | 2022-05-17 12:37:06 +0300 |
|---|---|---|
| committer | Marc Zyngier <maz@kernel.org> | 2022-05-17 12:37:06 +0300 |
| commit | 492449ae4f0ad96948c3e029ca00736a7f1b3d77 (patch) | |
| tree | fb37185cef4cc5a3d625f1f2d4714129fe59cdee /arch/arm | |
| parent | 61299e1838b70045ab3ddd9c439a3f3966c9f52a (diff) | |
| parent | 614ab80c96474682157cabb14f8c8602b3422e90 (diff) | |
| download | linux-492449ae4f0ad96948c3e029ca00736a7f1b3d77.tar.xz | |
Merge branch irq/gic-v3-nmi-fixes-5.19 into irq/irqchip-next
* irq/gic-v3-nmi-fixes-5.19:
: .
: GICv3 pseudo-NMI fixes from Mark Rutland:
:
: "These patches fix a couple of issues with the way GICv3 pseudo-NMIs are
: handled:
:
: * The first patch adds a barrier we missed from NMI handling due to an
: oversight.
:
: * The second patch refactors some logic around reads from ICC_IAR1_EL1
: and adds commentary to explain what's going on.
:
: * The third patch descends into madness, reworking gic_handle_irq() to
: consistently manage ICC_PMR_EL1 + DAIF and avoid cases where these can
: be left in an inconsistent state while softirqs are processed."
: .
irqchip/gic-v3: Fix priority mask handling
irqchip/gic-v3: Refactor ISB + EOIR at ack time
irqchip/gic-v3: Ensure pseudo-NMIs have an ISB between ack and handling
Signed-off-by: Marc Zyngier <maz@kernel.org>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/include/asm/arch_gicv3.h | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h index 413abfb42989..f82a819eb0db 100644 --- a/arch/arm/include/asm/arch_gicv3.h +++ b/arch/arm/include/asm/arch_gicv3.h @@ -48,6 +48,7 @@ static inline u32 read_ ## a64(void) \ return read_sysreg(a32); \ } \ +CPUIF_MAP(ICC_EOIR1, ICC_EOIR1_EL1) CPUIF_MAP(ICC_PMR, ICC_PMR_EL1) CPUIF_MAP(ICC_AP0R0, ICC_AP0R0_EL1) CPUIF_MAP(ICC_AP0R1, ICC_AP0R1_EL1) @@ -63,12 +64,6 @@ CPUIF_MAP(ICC_AP1R3, ICC_AP1R3_EL1) /* Low-level accessors */ -static inline void gic_write_eoir(u32 irq) -{ - write_sysreg(irq, ICC_EOIR1); - isb(); -} - static inline void gic_write_dir(u32 val) { write_sysreg(val, ICC_DIR); |