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| author | Guo Ren <guoren@linux.alibaba.com> | 2020-09-07 09:20:18 +0300 |
|---|---|---|
| committer | Guo Ren <guoren@linux.alibaba.com> | 2021-01-12 04:52:40 +0300 |
| commit | 0c8a32eed1625a65798286fb73fea8710a908545 (patch) | |
| tree | 69992b6e217f5e985ebbf1f739b2af336d89138c /arch/csky/include/asm/pgtable.h | |
| parent | 7c53f6b671f4aba70ff15e1b05148b10d58c2837 (diff) | |
| download | linux-0c8a32eed1625a65798286fb73fea8710a908545.tar.xz | |
csky: Add memory layout 2.5G(user):1.5G(kernel)
There are two ways for translating va to pa for csky:
- Use TLB(Translate Lookup Buffer) and PTW (Page Table Walk)
- Use SSEG0/1 (Simple Segment Mapping)
We use tlb mapping 0-2G and 3G-4G virtual address area and SSEG0/1
are for 2G-2.5G and 2.5G-3G translation. We could disable SSEG0
to use 2G-2.5G as TLB user mapping.
Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Diffstat (limited to 'arch/csky/include/asm/pgtable.h')
| -rw-r--r-- | arch/csky/include/asm/pgtable.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/csky/include/asm/pgtable.h b/arch/csky/include/asm/pgtable.h index 2002cb7f1053..6ec97af0d1ff 100644 --- a/arch/csky/include/asm/pgtable.h +++ b/arch/csky/include/asm/pgtable.h @@ -14,7 +14,7 @@ #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) -#define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) +#define USER_PTRS_PER_PGD (PAGE_OFFSET/PGDIR_SIZE) #define FIRST_USER_ADDRESS 0UL /* |