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author | Huacai Chen <chenhuacai@loongson.cn> | 2022-05-31 13:04:11 +0300 |
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committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-06-03 15:09:28 +0300 |
commit | 09cfefb7fa70c3af011b0db0a513fd80b2f18abc (patch) | |
tree | fc1a269ecba1f88cabb2e79ee92251612ed6605a /arch/loongarch/include/asm/cache.h | |
parent | 803b0fc5c3f2baa6e54978cd576407896f789b08 (diff) | |
download | linux-09cfefb7fa70c3af011b0db0a513fd80b2f18abc.tar.xz |
LoongArch: Add memory management
Add memory management support for LoongArch, including: cache and tlb
management, page fault handling and ioremap/mmap support.
Reviewed-by: WANG Xuerui <git@xen0n.name>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm/cache.h')
-rw-r--r-- | arch/loongarch/include/asm/cache.h | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/cache.h b/arch/loongarch/include/asm/cache.h new file mode 100644 index 000000000000..1b6d09617199 --- /dev/null +++ b/arch/loongarch/include/asm/cache.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2020-2022 Loongson Technology Corporation Limited + */ +#ifndef _ASM_CACHE_H +#define _ASM_CACHE_H + +#define L1_CACHE_SHIFT CONFIG_L1_CACHE_SHIFT +#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) + +#define __read_mostly __section(".data..read_mostly") + +#endif /* _ASM_CACHE_H */ |