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| author | Huacai Chen <chenhuacai@loongson.cn> | 2022-10-12 11:36:14 +0300 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2022-10-12 11:36:14 +0300 |
| commit | b61a40afca164a9bd066f749beff3bf209c5e209 (patch) | |
| tree | 414693038d707d37b34edfee4f4ece650275996a /arch/loongarch/include/asm/cpu-features.h | |
| parent | a2a84e36331af3b000ad12b552c5485b8282b366 (diff) | |
| download | linux-b61a40afca164a9bd066f749beff3bf209c5e209.tar.xz | |
LoongArch: Refactor cache probe and flush methods
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.
However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm/cpu-features.h')
| -rw-r--r-- | arch/loongarch/include/asm/cpu-features.h | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/arch/loongarch/include/asm/cpu-features.h b/arch/loongarch/include/asm/cpu-features.h index a8d87c40a0eb..b07974218393 100644 --- a/arch/loongarch/include/asm/cpu-features.h +++ b/arch/loongarch/include/asm/cpu-features.h @@ -19,11 +19,6 @@ #define cpu_has_loongarch32 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_32BIT) #define cpu_has_loongarch64 (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT) -#define cpu_icache_line_size() cpu_data[0].icache.linesz -#define cpu_dcache_line_size() cpu_data[0].dcache.linesz -#define cpu_vcache_line_size() cpu_data[0].vcache.linesz -#define cpu_scache_line_size() cpu_data[0].scache.linesz - #ifdef CONFIG_32BIT # define cpu_has_64bits (cpu_data[0].isa_level & LOONGARCH_CPU_ISA_64BIT) # define cpu_vabits 31 |