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| author | Qing Zhang <zhangqing@loongson.cn> | 2023-02-25 10:52:57 +0300 |
|---|---|---|
| committer | Huacai Chen <chenhuacai@loongson.cn> | 2023-02-25 17:12:17 +0300 |
| commit | 424421a7f34c1222d20a6c279f13b9caa71ecc83 (patch) | |
| tree | 5a758519364a4b1d2973ada95e98077bde4c6c33 /arch/loongarch/include/asm/ptrace.h | |
| parent | 356bd6f23682f11f7afe923d86c7f5f852b97fb2 (diff) | |
| download | linux-424421a7f34c1222d20a6c279f13b9caa71ecc83.tar.xz | |
LoongArch: ptrace: Add hardware single step support
Use the generic ptrace_resume code for PTRACE_SYSCALL, PTRACE_CONT,
PTRACE_KILL and PTRACE_SINGLESTEP handling. This implies defining
arch_has_single_step() and implementing the user_enable_single_step()
and user_disable_single_step() functions.
LoongArch cannot do hardware single-stepping per se, the hardware
single-stepping it is achieved by configuring the instruction fetch
watchpoints (FWPS) and specifies that the next instruction must trigger
the watch exception by setting the mask bit. In some scenarios
CSR.FWPS.Skip is used to ignore the next hit result, avoid endless
repeated triggering of the same watchpoint without canceling it.
Signed-off-by: Qing Zhang <zhangqing@loongson.cn>
Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
Diffstat (limited to 'arch/loongarch/include/asm/ptrace.h')
| -rw-r--r-- | arch/loongarch/include/asm/ptrace.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/loongarch/include/asm/ptrace.h b/arch/loongarch/include/asm/ptrace.h index 5d3872131866..6eab4393b108 100644 --- a/arch/loongarch/include/asm/ptrace.h +++ b/arch/loongarch/include/asm/ptrace.h @@ -183,4 +183,8 @@ static inline void user_stack_pointer_set(struct pt_regs *regs, regs->regs[3] = val; } +#ifdef CONFIG_HAVE_HW_BREAKPOINT +#define arch_has_single_step() (1) +#endif + #endif /* _ASM_PTRACE_H */ |