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authorLinus Torvalds <torvalds@linux-foundation.org>2015-02-22 06:41:38 +0300
committerLinus Torvalds <torvalds@linux-foundation.org>2015-02-22 06:41:38 +0300
commita135c717d5cdb311cff7661af4c17fef0562e590 (patch)
tree830a276ee80b95f02ae243c641690c9f2014922d /arch/mips/alchemy
parent21770332330800194cb9a76f802e9c77bcb690d3 (diff)
parent44923c9cfa1a32c5a4013cb4b4853ddcdcd59142 (diff)
downloadlinux-a135c717d5cdb311cff7661af4c17fef0562e590.tar.xz
Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle: "This is the main pull request for MIPS: - a number of fixes that didn't make the 3.19 release. - a number of cleanups. - preliminary support for Cavium's Octeon 3 SOCs which feature up to 48 MIPS64 R3 cores with FPU and hardware virtualization. - support for MIPS R6 processors. Revision 6 of the MIPS architecture is a major revision of the MIPS architecture which does away with many of original sins of the architecture such as branch delay slots. This and other changes in R6 require major changes throughout the entire MIPS core architecture code and make up for the lion share of this pull request. - finally some preparatory work for eXtendend Physical Address support, which allows support of up to 40 bit of physical address space on 32 bit processors" [ Ahh, MIPS can't leave the PAE brain damage alone. It's like every CPU architect has to make that mistake, but pee in the snow by changing the TLA. But whether it's called PAE, LPAE or XPA, it's horrid crud - Linus ] * 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (114 commits) MIPS: sead3: Corrected get_c0_perfcount_int MIPS: mm: Remove dead macro definitions MIPS: OCTEON: irq: add CIB and other fixes MIPS: OCTEON: Don't do acknowledge operations for level triggered irqs. MIPS: OCTEON: More OCTEONIII support MIPS: OCTEON: Remove setting of processor specific CVMCTL icache bits. MIPS: OCTEON: Core-15169 Workaround and general CVMSEG cleanup. MIPS: OCTEON: Update octeon-model.h code for new SoCs. MIPS: OCTEON: Implement DCache errata workaround for all CN6XXX MIPS: OCTEON: Add little-endian support to asm/octeon/octeon.h MIPS: OCTEON: Implement the core-16057 workaround MIPS: OCTEON: Delete unused COP2 saving code MIPS: OCTEON: Use correct instruction to read 64-bit COP0 register MIPS: OCTEON: Save and restore CP2 SHA3 state MIPS: OCTEON: Fix FP context save. MIPS: OCTEON: Save/Restore wider multiply registers in OCTEON III CPUs MIPS: boot: Provide more uImage options MIPS: Remove unneeded #ifdef __KERNEL__ from asm/processor.h MIPS: ip22-gio: Remove legacy suspend/resume support mips: pci: Add ifdef around pci_proc_domain ...
Diffstat (limited to 'arch/mips/alchemy')
-rw-r--r--arch/mips/alchemy/common/clock.c27
-rw-r--r--arch/mips/alchemy/common/setup.c4
2 files changed, 25 insertions, 6 deletions
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 604b7d009d8d..6a98d2cb402c 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -127,12 +127,20 @@ static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
t = 396000000;
else {
t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
+ if (alchemy_get_cputype() < ALCHEMY_CPU_AU1300)
+ t &= 0x3f;
t *= parent_rate;
}
return t;
}
+void __init alchemy_set_lpj(void)
+{
+ preset_lpj = alchemy_clk_cpu_recalc(NULL, ALCHEMY_ROOTCLK_RATE);
+ preset_lpj /= 2 * HZ;
+}
+
static struct clk_ops alchemy_clkops_cpu = {
.recalc_rate = alchemy_clk_cpu_recalc,
};
@@ -315,17 +323,26 @@ static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
/* lrclk: external synchronous static bus clock ***********************/
-static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
+static struct clk __init *alchemy_clk_setup_lrclk(const char *pn, int t)
{
- /* MEM_STCFG0[15:13] = divisor.
+ /* Au1000, Au1500: MEM_STCFG0[11]: If bit is set, lrclk=pclk/5,
+ * otherwise lrclk=pclk/4.
+ * All other variants: MEM_STCFG0[15:13] = divisor.
* L/RCLK = periph_clk / (divisor + 1)
* On Au1000, Au1500, Au1100 it's called LCLK,
* on later models it's called RCLK, but it's the same thing.
*/
struct clk *c;
- unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
+ unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0);
- v = (v & 7) + 1;
+ switch (t) {
+ case ALCHEMY_CPU_AU1000:
+ case ALCHEMY_CPU_AU1500:
+ v = 4 + ((v >> 11) & 1);
+ break;
+ default: /* all other models */
+ v = ((v >> 13) & 7) + 1;
+ }
c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
pn, 0, 1, v);
if (!IS_ERR(c))
@@ -1066,7 +1083,7 @@ static int __init alchemy_clk_init(void)
ERRCK(c)
/* L/RCLK: external static bus clock for synchronous mode */
- c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
+ c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK, ctype);
ERRCK(c)
/* Frequency dividers 0-5 */
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 4e72daf12c32..2902138b3e0f 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -34,10 +34,12 @@
#include <au1000.h>
extern void __init board_setup(void);
-extern void set_cpuspec(void);
+extern void __init alchemy_set_lpj(void);
void __init plat_mem_setup(void)
{
+ alchemy_set_lpj();
+
if (au1xxx_cpu_needs_config_od())
/* Various early Au1xx0 errata corrected by this */
set_c0_config(1 << 19); /* Set Config[OD] */