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| author | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-03-23 15:06:43 +0400 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab@redhat.com> | 2012-03-23 15:06:43 +0400 |
| commit | 7483d45f0aee3afc0646d185cabd4af9f6cab58c (patch) | |
| tree | a312f7d77c34748bec62f0431df33007b10e4e7f /arch/mips/ath79/irq.c | |
| parent | 3e85fc1b9fc1c7e20b9a01f2314bb633bb10501a (diff) | |
| parent | f92c97c8bd77992ff8bd6ef29a23dc82dca799cb (diff) | |
| download | linux-7483d45f0aee3afc0646d185cabd4af9f6cab58c.tar.xz | |
Merge branch 'staging/for_v3.4' into v4l_for_linus
* staging/for_v3.4: (10117 commits)
[media] update CARDLIST.em28xx
[media] partially reverts changeset fa5527c
[media] stb0899: fix the limits for signal strength values
[media] em28xx: support for 2304:0242 PCTV QuatroStick (510e)
[media] em28xx: support for 2013:0251 PCTV QuatroStick nano (520e)
[media] -EINVAL -> -ENOTTY
[media] gspca - sn9c20x: Cleanup source
[media] gspca - sn9c20x: Simplify register write for capture start/stop
[media] gspca - sn9c20x: Add automatic JPEG compression mechanism
[media] gspca - sn9c20x: Greater delay in case of sensor no response
[media] gspca - sn9c20x: Optimize the code of write sequences
[media] gspca - sn9c20x: Add the JPEG compression quality control
[media] gspca - sn9c20x: Add a delay after Omnivision sensor reset
[media] gspca - sn9c20x: Propagate USB errors to higher level
[media] gspca - sn9c20x: Use the new video control mechanism
[media] gspca - sn9c20x: Fix loss of frame start
[media] gspca - zc3xx: Lack of register 08 value for sensor cs2102k
[media] gspca - ov534_9: Add brightness to OmniVision 5621 sensor
[media] gspca - zc3xx: Add V4L2_CID_JPEG_COMPRESSION_QUALITY control support
[media] pvrusb2: fix 7MHz & 8MHz DVB-T tuner support for HVR1900 rev D1F5
...
Diffstat (limited to 'arch/mips/ath79/irq.c')
| -rw-r--r-- | arch/mips/ath79/irq.c | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c index ac610d5fe3ba..1b073de44680 100644 --- a/arch/mips/ath79/irq.c +++ b/arch/mips/ath79/irq.c @@ -46,6 +46,15 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) else if (pending & MISC_INT_TIMER) generic_handle_irq(ATH79_MISC_IRQ_TIMER); + else if (pending & MISC_INT_TIMER2) + generic_handle_irq(ATH79_MISC_IRQ_TIMER2); + + else if (pending & MISC_INT_TIMER3) + generic_handle_irq(ATH79_MISC_IRQ_TIMER3); + + else if (pending & MISC_INT_TIMER4) + generic_handle_irq(ATH79_MISC_IRQ_TIMER4); + else if (pending & MISC_INT_OHCI) generic_handle_irq(ATH79_MISC_IRQ_OHCI); @@ -58,6 +67,9 @@ static void ath79_misc_irq_handler(unsigned int irq, struct irq_desc *desc) else if (pending & MISC_INT_WDOG) generic_handle_irq(ATH79_MISC_IRQ_WDOG); + else if (pending & MISC_INT_ETHSW) + generic_handle_irq(ATH79_MISC_IRQ_ETHSW); + else spurious_interrupt(); } @@ -117,7 +129,7 @@ static void __init ath79_misc_irq_init(void) if (soc_is_ar71xx() || soc_is_ar913x()) ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; - else if (soc_is_ar724x()) + else if (soc_is_ar724x() || soc_is_ar933x()) ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; else BUG(); @@ -174,6 +186,9 @@ void __init arch_init_irq(void) } else if (soc_is_ar913x()) { ath79_ip2_flush_reg = AR913X_DDR_REG_FLUSH_WMAC; ath79_ip3_flush_reg = AR913X_DDR_REG_FLUSH_USB; + } else if (soc_is_ar933x()) { + ath79_ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC; + ath79_ip3_flush_reg = AR933X_DDR_REG_FLUSH_USB; } else BUG(); |