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authorManuel Lauss <manuel.lauss@gmail.com>2014-07-23 18:36:25 +0400
committerRalf Baechle <ralf@linux-mips.org>2014-07-30 15:53:52 +0400
commit9cf12167e909a86fbc4b39cf4cffef4cba40f1b3 (patch)
tree034c96710ea6f4fb1de8c47d0132c585c8013693 /arch/mips/include/asm/mach-au1x00
parent1d09de7dc76ef96a9a2c7c0244e20f12d68e6ef8 (diff)
downloadlinux-9cf12167e909a86fbc4b39cf4cffef4cba40f1b3.tar.xz
MIPS: Alchemy: add helpers to access static memory ctrl registers.
This patch changes the static memory controller registers to offsets from base, prefixes them with AU1000_ to avoid silent failures due to changed addresses and introduces helpers to access them. No functional changes, comparing assembly of a few select functions shows no differences. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/7463/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mach-au1x00')
-rw-r--r--arch/mips/include/asm/mach-au1x00/au1000.h50
1 files changed, 31 insertions, 19 deletions
diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h
index c8cfca9c3167..d664b11e0baf 100644
--- a/arch/mips/include/asm/mach-au1x00/au1000.h
+++ b/arch/mips/include/asm/mach-au1x00/au1000.h
@@ -309,25 +309,21 @@
#define AU1550_MEM_SDSREF 0x08D0
#define AU1550_MEM_SDSLEEP MEM_SDSREF
-/* Static Bus Controller */
-#define MEM_STCFG0 0xB4001000
-#define MEM_STTIME0 0xB4001004
-#define MEM_STADDR0 0xB4001008
-
-#define MEM_STCFG1 0xB4001010
-#define MEM_STTIME1 0xB4001014
-#define MEM_STADDR1 0xB4001018
-
-#define MEM_STCFG2 0xB4001020
-#define MEM_STTIME2 0xB4001024
-#define MEM_STADDR2 0xB4001028
-
-#define MEM_STCFG3 0xB4001030
-#define MEM_STTIME3 0xB4001034
-#define MEM_STADDR3 0xB4001038
-
-#define MEM_STNDCTL 0xB4001100
-#define MEM_STSTAT 0xB4001104
+/* Static Bus Controller register offsets */
+#define AU1000_MEM_STCFG0 0x000
+#define AU1000_MEM_STTIME0 0x004
+#define AU1000_MEM_STADDR0 0x008
+#define AU1000_MEM_STCFG1 0x010
+#define AU1000_MEM_STTIME1 0x014
+#define AU1000_MEM_STADDR1 0x018
+#define AU1000_MEM_STCFG2 0x020
+#define AU1000_MEM_STTIME2 0x024
+#define AU1000_MEM_STADDR2 0x028
+#define AU1000_MEM_STCFG3 0x030
+#define AU1000_MEM_STTIME3 0x034
+#define AU1000_MEM_STADDR3 0x038
+#define AU1000_MEM_STNDCTL 0x100
+#define AU1000_MEM_STSTAT 0x104
#define MEM_STNAND_CMD 0x0
#define MEM_STNAND_ADDR 0x4
@@ -713,6 +709,22 @@ static inline void alchemy_wrsys(unsigned long v, int regofs)
wmb(); /* drain writebuffer */
}
+/* helpers to access static memctrl registers */
+static inline unsigned long alchemy_rdsmem(int regofs)
+{
+ void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
+
+ return __raw_readl(b + regofs);
+}
+
+static inline void alchemy_wrsmem(unsigned long v, int regofs)
+{
+ void __iomem *b = (void __iomem *)KSEG1ADDR(AU1000_STATIC_MEM_PHYS_ADDR);
+
+ __raw_writel(v, b + regofs);
+ wmb(); /* drain writebuffer */
+}
+
/* Early Au1000 have a write-only SYS_CPUPLL register. */
static inline int au1xxx_cpu_has_pll_wo(void)
{