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| author | Paul Burton <paul.burton@mips.com> | 2019-02-02 04:43:27 +0300 |
|---|---|---|
| committer | Paul Burton <paul.burton@mips.com> | 2019-02-04 21:56:35 +0300 |
| commit | 535113896e802e9f8f92c05a887d1761c34ae903 (patch) | |
| tree | 4d0b573a5ad008f478f806e585aec22db77e03cc /arch/mips/include/asm/mipsregs.h | |
| parent | 0b317c389c6771cbe1c5a12fe9322285a808a9bd (diff) | |
| download | linux-535113896e802e9f8f92c05a887d1761c34ae903.tar.xz | |
MIPS: Add GINVT instruction helpers
Add a family of ginvt_* functions making it easy to emit a GINVT
instruction to globally invalidate TLB entries. We make use of the
_ASM_MACRO infrastructure to support emitting the instructions even if
the assembler isn't new enough to support them natively.
An associated STYPE_GINV definition & sync_ginv() function are added to
emit a sync instruction of type 0x14, which operates as a completion
barrier for these new GINVT (and GINVI) instructions.
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: linux-mips@vger.kernel.org
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 402b80af91aa..900a47581dd1 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1247,6 +1247,13 @@ __asm__(".macro parse_r var r\n\t" ENC \ ".endm") +/* Instructions with 1 register operand & 1 immediate operand */ +#define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \ + __asm__(".macro " #OP " " #R1 ", " #I2 "\n\t" \ + "parse_r __" #R1 ", \\" #R1 "\n\t" \ + ENC \ + ".endm") + /* Instructions with 2 register operands */ #define _ASM_MACRO_2R(OP, R1, R2, ENC) \ __asm__(".macro " #OP " " #R1 ", " #R2 "\n\t" \ |