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| author | Maciej W. Rozycki <macro@linux-mips.org> | 2015-04-04 01:27:38 +0300 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2015-04-08 02:10:31 +0300 |
| commit | f1f3b7ebac08161761c352fd070cfa07b7b94c54 (patch) | |
| tree | bd02705eb60a81da45d40827dcfec70dd31ab622 /arch/mips/include/asm/mipsregs.h | |
| parent | c491cfa2ca804e58f4e88386736c1608c82da08a (diff) | |
| download | linux-f1f3b7ebac08161761c352fd070cfa07b7b94c54.tar.xz | |
MIPS: math-emu: Define IEEE 754-2008 feature control bits
Define IEEE 754-2008 feature control bits: FIR.HAS2008, FCSR.ABS2008 and
FCSR.NAN2008, and update the `_ieee754_csr' structure accordingly.
For completeness define FIR.UFRP too.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9709/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm/mipsregs.h')
| -rw-r--r-- | arch/mips/include/asm/mipsregs.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 120f2225ed3f..764e2756b54d 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -708,6 +708,8 @@ #define MIPS_FPIR_W (_ULCAST_(1) << 20) #define MIPS_FPIR_L (_ULCAST_(1) << 21) #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) +#define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23) +#define MIPS_FPIR_UFRP (_ULCAST_(1) << 28) #define MIPS_FPIR_FREP (_ULCAST_(1) << 29) /* @@ -765,10 +767,13 @@ #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S) /* - * Bits 18 - 20 of the FPU Status Register will be read as 0, + * Bits 22:20 of the FPU Status Register will be read as 0, * and should be written as zero. */ -#define FPU_CSR_RSVD 0x001c0000 +#define FPU_CSR_RSVD (_ULCAST_(7) << 20) + +#define FPU_CSR_ABS2008 (_ULCAST_(1) << 19) +#define FPU_CSR_NAN2008 (_ULCAST_(1) << 18) /* * X the exception cause indicator |