diff options
author | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2021-10-20 15:49:13 +0300 |
---|---|---|
committer | Thomas Bogendoerfer <tsbogend@alpha.franken.de> | 2021-10-24 18:24:47 +0300 |
commit | 95b8a5e0111a47e5ef780c04cb6293be33d6ee0d (patch) | |
tree | 0c54fd731b6ba11ed813b9225b4484042e281c71 /arch/mips/pci | |
parent | 626bfa03729959ea9917181fb3d8ffaa1594d02a (diff) | |
download | linux-95b8a5e0111a47e5ef780c04cb6293be33d6ee0d.tar.xz |
MIPS: Remove NETLOGIC support
No (active) developer owns this hardware, so let's remove Linux support.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Diffstat (limited to 'arch/mips/pci')
-rw-r--r-- | arch/mips/pci/Makefile | 3 | ||||
-rw-r--r-- | arch/mips/pci/msi-xlp.c | 571 | ||||
-rw-r--r-- | arch/mips/pci/pci-xlp.c | 332 | ||||
-rw-r--r-- | arch/mips/pci/pci-xlr.c | 368 |
4 files changed, 0 insertions, 1274 deletions
diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index f3eecc065e5c..6ddefafd00cb 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -56,10 +56,7 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o obj-$(CONFIG_CAVIUM_OCTEON_SOC) += pci-octeon.o pcie-octeon.o -obj-$(CONFIG_CPU_XLR) += pci-xlr.o -obj-$(CONFIG_CPU_XLP) += pci-xlp.o ifdef CONFIG_PCI_MSI obj-$(CONFIG_CAVIUM_OCTEON_SOC) += msi-octeon.o -obj-$(CONFIG_CPU_XLP) += msi-xlp.o endif diff --git a/arch/mips/pci/msi-xlp.c b/arch/mips/pci/msi-xlp.c deleted file mode 100644 index bb14335f804b..000000000000 --- a/arch/mips/pci/msi-xlp.c +++ /dev/null @@ -1,571 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/msi.h> -#include <linux/mm.h> -#include <linux/irq.h> -#include <linux/irqdesc.h> -#include <linux/console.h> - -#include <asm/io.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/mips-extns.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/pcibus.h> -#include <asm/netlogic/xlp-hal/bridge.h> - -#define XLP_MSIVEC_PER_LINK 32 -#define XLP_MSIXVEC_TOTAL (cpu_is_xlp9xx() ? 128 : 32) -#define XLP_MSIXVEC_PER_LINK (cpu_is_xlp9xx() ? 32 : 8) - -/* 128 MSI irqs per node, mapped starting at NLM_MSI_VEC_BASE */ -static inline int nlm_link_msiirq(int link, int msivec) -{ - return NLM_MSI_VEC_BASE + link * XLP_MSIVEC_PER_LINK + msivec; -} - -/* get the link MSI vector from irq number */ -static inline int nlm_irq_msivec(int irq) -{ - return (irq - NLM_MSI_VEC_BASE) % XLP_MSIVEC_PER_LINK; -} - -/* get the link from the irq number */ -static inline int nlm_irq_msilink(int irq) -{ - int total_msivec = XLP_MSIVEC_PER_LINK * PCIE_NLINKS; - - return ((irq - NLM_MSI_VEC_BASE) % total_msivec) / - XLP_MSIVEC_PER_LINK; -} - -/* - * For XLP 8xx/4xx/3xx/2xx, only 32 MSI-X vectors are possible because - * there are only 32 PIC interrupts for MSI. We split them statically - * and use 8 MSI-X vectors per link - this keeps the allocation and - * lookup simple. - * On XLP 9xx, there are 32 vectors per link, and the interrupts are - * not routed thru PIC, so we can use all 128 MSI-X vectors. - */ -static inline int nlm_link_msixirq(int link, int bit) -{ - return NLM_MSIX_VEC_BASE + link * XLP_MSIXVEC_PER_LINK + bit; -} - -/* get the link MSI vector from irq number */ -static inline int nlm_irq_msixvec(int irq) -{ - return (irq - NLM_MSIX_VEC_BASE) % XLP_MSIXVEC_TOTAL; -} - -/* get the link from MSIX vec */ -static inline int nlm_irq_msixlink(int msixvec) -{ - return msixvec / XLP_MSIXVEC_PER_LINK; -} - -/* - * Per link MSI and MSI-X information, set as IRQ handler data for - * MSI and MSI-X interrupts. - */ -struct xlp_msi_data { - struct nlm_soc_info *node; - uint64_t lnkbase; - uint32_t msi_enabled_mask; - uint32_t msi_alloc_mask; - uint32_t msix_alloc_mask; - spinlock_t msi_lock; -}; - -/* - * MSI Chip definitions - * - * On XLP, there is a PIC interrupt associated with each PCIe link on the - * chip (which appears as a PCI bridge to us). This gives us 32 MSI irqa - * per link and 128 overall. - * - * When a device connected to the link raises a MSI interrupt, we get a - * link interrupt and we then have to look at PCIE_MSI_STATUS register at - * the bridge to map it to the IRQ - */ -static void xlp_msi_enable(struct irq_data *d) -{ - struct xlp_msi_data *md = irq_data_get_irq_chip_data(d); - unsigned long flags; - int vec; - - vec = nlm_irq_msivec(d->irq); - spin_lock_irqsave(&md->msi_lock, flags); - md->msi_enabled_mask |= 1u << vec; - if (cpu_is_xlp9xx()) - nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN, - md->msi_enabled_mask); - else - nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask); - spin_unlock_irqrestore(&md->msi_lock, flags); -} - -static void xlp_msi_disable(struct irq_data *d) -{ - struct xlp_msi_data *md = irq_data_get_irq_chip_data(d); - unsigned long flags; - int vec; - - vec = nlm_irq_msivec(d->irq); - spin_lock_irqsave(&md->msi_lock, flags); - md->msi_enabled_mask &= ~(1u << vec); - if (cpu_is_xlp9xx()) - nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN, - md->msi_enabled_mask); - else - nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask); - spin_unlock_irqrestore(&md->msi_lock, flags); -} - -static void xlp_msi_mask_ack(struct irq_data *d) -{ - struct xlp_msi_data *md = irq_data_get_irq_chip_data(d); - int link, vec; - - link = nlm_irq_msilink(d->irq); - vec = nlm_irq_msivec(d->irq); - xlp_msi_disable(d); - - /* Ack MSI on bridge */ - if (cpu_is_xlp9xx()) - nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec); - else - nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec); - -} - -static struct irq_chip xlp_msi_chip = { - .name = "XLP-MSI", - .irq_enable = xlp_msi_enable, - .irq_disable = xlp_msi_disable, - .irq_mask_ack = xlp_msi_mask_ack, - .irq_unmask = xlp_msi_enable, -}; - -/* - * XLP8XX/4XX/3XX/2XX: - * The MSI-X interrupt handling is different from MSI, there are 32 MSI-X - * interrupts generated by the PIC and each of these correspond to a MSI-X - * vector (0-31) that can be assigned. - * - * We divide the MSI-X vectors to 8 per link and do a per-link allocation - * - * XLP9XX: - * 32 MSI-X vectors are available per link, and the interrupts are not routed - * thru the PIC. PIC ack not needed. - * - * Enable and disable done using standard MSI functions. - */ -static void xlp_msix_mask_ack(struct irq_data *d) -{ - struct xlp_msi_data *md; - int link, msixvec; - uint32_t status_reg, bit; - - msixvec = nlm_irq_msixvec(d->irq); - link = nlm_irq_msixlink(msixvec); - pci_msi_mask_irq(d); - md = irq_data_get_irq_chip_data(d); - - /* Ack MSI on bridge */ - if (cpu_is_xlp9xx()) { - status_reg = PCIE_9XX_MSIX_STATUSX(link); - bit = msixvec % XLP_MSIXVEC_PER_LINK; - } else { - status_reg = PCIE_MSIX_STATUS; - bit = msixvec; - } - nlm_write_reg(md->lnkbase, status_reg, 1u << bit); - - if (!cpu_is_xlp9xx()) - nlm_pic_ack(md->node->picbase, - PIC_IRT_PCIE_MSIX_INDEX(msixvec)); -} - -static struct irq_chip xlp_msix_chip = { - .name = "XLP-MSIX", - .irq_enable = pci_msi_unmask_irq, - .irq_disable = pci_msi_mask_irq, - .irq_mask_ack = xlp_msix_mask_ack, - .irq_unmask = pci_msi_unmask_irq, -}; - -void arch_teardown_msi_irq(unsigned int irq) -{ -} - -/* - * Setup a PCIe link for MSI. By default, the links are in - * legacy interrupt mode. We will switch them to MSI mode - * at the first MSI request. - */ -static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr) -{ - u32 val; - - if (cpu_is_xlp9xx()) { - val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0); - if ((val & 0x200) == 0) { - val |= 0x200; /* MSI Interrupt enable */ - nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val); - } - } else { - val = nlm_read_reg(lnkbase, PCIE_INT_EN0); - if ((val & 0x200) == 0) { - val |= 0x200; - nlm_write_reg(lnkbase, PCIE_INT_EN0, val); - } - } - - val = nlm_read_reg(lnkbase, 0x1); /* CMD */ - if ((val & 0x0400) == 0) { - val |= 0x0400; - nlm_write_reg(lnkbase, 0x1, val); - } - - /* Update IRQ in the PCI irq reg */ - val = nlm_read_pci_reg(lnkbase, 0xf); - val &= ~0x1fu; - val |= (1 << 8) | lirq; - nlm_write_pci_reg(lnkbase, 0xf, val); - - /* MSI addr */ - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32); - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff); - - /* MSI cap for bridge */ - val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP); - if ((val & (1 << 16)) == 0) { - val |= 0xb << 16; /* mmc32, msi enable */ - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val); - } -} - -/* - * Allocate a MSI vector on a link - */ -static int xlp_setup_msi(uint64_t lnkbase, int node, int link, - struct msi_desc *desc) -{ - struct xlp_msi_data *md; - struct msi_msg msg; - unsigned long flags; - int msivec, irt, lirq, xirq, ret; - uint64_t msiaddr; - - /* Get MSI data for the link */ - lirq = PIC_PCIE_LINK_MSI_IRQ(link); - xirq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); - md = irq_get_chip_data(xirq); - msiaddr = MSI_LINK_ADDR(node, link); - - spin_lock_irqsave(&md->msi_lock, flags); - if (md->msi_alloc_mask == 0) { - xlp_config_link_msi(lnkbase, lirq, msiaddr); - /* switch the link IRQ to MSI range */ - if (cpu_is_xlp9xx()) - irt = PIC_9XX_IRT_PCIE_LINK_INDEX(link); - else - irt = PIC_IRT_PCIE_LINK_INDEX(link); - nlm_setup_pic_irq(node, lirq, lirq, irt); - nlm_pic_init_irt(nlm_get_node(node)->picbase, irt, lirq, - node * nlm_threads_per_node(), 1 /*en */); - } - - /* allocate a MSI vec, and tell the bridge about it */ - msivec = fls(md->msi_alloc_mask); - if (msivec == XLP_MSIVEC_PER_LINK) { - spin_unlock_irqrestore(&md->msi_lock, flags); - return -ENOMEM; - } - md->msi_alloc_mask |= (1u << msivec); - spin_unlock_irqrestore(&md->msi_lock, flags); - - msg.address_hi = msiaddr >> 32; - msg.address_lo = msiaddr & 0xffffffff; - msg.data = 0xc00 | msivec; - - xirq = xirq + msivec; /* msi mapped to global irq space */ - ret = irq_set_msi_desc(xirq, desc); - if (ret < 0) - return ret; - - pci_write_msi_msg(xirq, &msg); - return 0; -} - -/* - * Switch a link to MSI-X mode - */ -static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr) -{ - u32 val; - - val = nlm_read_reg(lnkbase, 0x2C); - if ((val & 0x80000000U) == 0) { - val |= 0x80000000U; - nlm_write_reg(lnkbase, 0x2C, val); - } - - if (cpu_is_xlp9xx()) { - val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0); - if ((val & 0x200) == 0) { - val |= 0x200; /* MSI Interrupt enable */ - nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val); - } - } else { - val = nlm_read_reg(lnkbase, PCIE_INT_EN0); - if ((val & 0x200) == 0) { - val |= 0x200; /* MSI Interrupt enable */ - nlm_write_reg(lnkbase, PCIE_INT_EN0, val); - } - } - - val = nlm_read_reg(lnkbase, 0x1); /* CMD */ - if ((val & 0x0400) == 0) { - val |= 0x0400; - nlm_write_reg(lnkbase, 0x1, val); - } - - /* Update IRQ in the PCI irq reg */ - val = nlm_read_pci_reg(lnkbase, 0xf); - val &= ~0x1fu; - val |= (1 << 8) | lirq; - nlm_write_pci_reg(lnkbase, 0xf, val); - - if (cpu_is_xlp9xx()) { - /* MSI-X addresses */ - nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE, - msixaddr >> 8); - nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT, - (msixaddr + MSI_ADDR_SZ) >> 8); - } else { - /* MSI-X addresses */ - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE, - msixaddr >> 8); - nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT, - (msixaddr + MSI_ADDR_SZ) >> 8); - } -} - -/* - * Allocate a MSI-X vector - */ -static int xlp_setup_msix(uint64_t lnkbase, int node, int link, - struct msi_desc *desc) -{ - struct xlp_msi_data *md; - struct msi_msg msg; - unsigned long flags; - int t, msixvec, lirq, xirq, ret; - uint64_t msixaddr; - - /* Get MSI data for the link */ - lirq = PIC_PCIE_MSIX_IRQ(link); - xirq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0)); - md = irq_get_chip_data(xirq); - msixaddr = MSIX_LINK_ADDR(node, link); - - spin_lock_irqsave(&md->msi_lock, flags); - /* switch the PCIe link to MSI-X mode at the first alloc */ - if (md->msix_alloc_mask == 0) - xlp_config_link_msix(lnkbase, lirq, msixaddr); - - /* allocate a MSI-X vec, and tell the bridge about it */ - t = fls(md->msix_alloc_mask); - if (t == XLP_MSIXVEC_PER_LINK) { - spin_unlock_irqrestore(&md->msi_lock, flags); - return -ENOMEM; - } - md->msix_alloc_mask |= (1u << t); - spin_unlock_irqrestore(&md->msi_lock, flags); - - xirq += t; - msixvec = nlm_irq_msixvec(xirq); - - msg.address_hi = msixaddr >> 32; - msg.address_lo = msixaddr & 0xffffffff; - msg.data = 0xc00 | msixvec; - - ret = irq_set_msi_desc(xirq, desc); - if (ret < 0) - return ret; - - pci_write_msi_msg(xirq, &msg); - return 0; -} - -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) -{ - struct pci_dev *lnkdev; - uint64_t lnkbase; - int node, link, slot; - - lnkdev = xlp_get_pcie_link(dev); - if (lnkdev == NULL) { - dev_err(&dev->dev, "Could not find bridge\n"); - return 1; - } - slot = PCI_SLOT(lnkdev->devfn); - link = PCI_FUNC(lnkdev->devfn); - node = slot / 8; - lnkbase = nlm_get_pcie_base(node, link); - - if (desc->msi_attrib.is_msix) - return xlp_setup_msix(lnkbase, node, link, desc); - else - return xlp_setup_msi(lnkbase, node, link, desc); -} - -void __init xlp_init_node_msi_irqs(int node, int link) -{ - struct nlm_soc_info *nodep; - struct xlp_msi_data *md; - int irq, i, irt, msixvec, val; - - pr_info("[%d %d] Init node PCI IRT\n", node, link); - nodep = nlm_get_node(node); - - /* Alloc an MSI block for the link */ - md = kzalloc(sizeof(*md), GFP_KERNEL); - spin_lock_init(&md->msi_lock); - md->msi_enabled_mask = 0; - md->msi_alloc_mask = 0; - md->msix_alloc_mask = 0; - md->node = nodep; - md->lnkbase = nlm_get_pcie_base(node, link); - - /* extended space for MSI interrupts */ - irq = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); - for (i = irq; i < irq + XLP_MSIVEC_PER_LINK; i++) { - irq_set_chip_and_handler(i, &xlp_msi_chip, handle_level_irq); - irq_set_chip_data(i, md); - } - - for (i = 0; i < XLP_MSIXVEC_PER_LINK ; i++) { - if (cpu_is_xlp9xx()) { - val = ((node * nlm_threads_per_node()) << 7 | - PIC_PCIE_MSIX_IRQ(link) << 1 | 0 << 0); - nlm_write_pcie_reg(md->lnkbase, PCIE_9XX_MSIX_VECX(i + - (link * XLP_MSIXVEC_PER_LINK)), val); - } else { - /* Initialize MSI-X irts to generate one interrupt - * per link - */ - msixvec = link * XLP_MSIXVEC_PER_LINK + i; - irt = PIC_IRT_PCIE_MSIX_INDEX(msixvec); - nlm_pic_init_irt(nodep->picbase, irt, - PIC_PCIE_MSIX_IRQ(link), - node * nlm_threads_per_node(), 1); - } - - /* Initialize MSI-X extended irq space for the link */ - irq = nlm_irq_to_xirq(node, nlm_link_msixirq(link, i)); - irq_set_chip_and_handler(irq, &xlp_msix_chip, handle_level_irq); - irq_set_chip_data(irq, md); - } -} - -void nlm_dispatch_msi(int node, int lirq) -{ - struct xlp_msi_data *md; - int link, i, irqbase; - u32 status; - - link = lirq - PIC_PCIE_LINK_MSI_IRQ_BASE; - irqbase = nlm_irq_to_xirq(node, nlm_link_msiirq(link, 0)); - md = irq_get_chip_data(irqbase); - if (cpu_is_xlp9xx()) - status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) & - md->msi_enabled_mask; - else - status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) & - md->msi_enabled_mask; - while (status) { - i = __ffs(status); - do_IRQ(irqbase + i); - status &= status - 1; - } - - /* Ack at eirr and PIC */ - ack_c0_eirr(PIC_PCIE_LINK_MSI_IRQ(link)); - if (cpu_is_xlp9xx()) - nlm_pic_ack(md->node->picbase, - PIC_9XX_IRT_PCIE_LINK_INDEX(link)); - else - nlm_pic_ack(md->node->picbase, PIC_IRT_PCIE_LINK_INDEX(link)); -} - -void nlm_dispatch_msix(int node, int lirq) -{ - struct xlp_msi_data *md; - int link, i, irqbase; - u32 status; - - link = lirq - PIC_PCIE_MSIX_IRQ_BASE; - irqbase = nlm_irq_to_xirq(node, nlm_link_msixirq(link, 0)); - md = irq_get_chip_data(irqbase); - if (cpu_is_xlp9xx()) - status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link)); - else - status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS); - - /* narrow it down to the MSI-x vectors for our link */ - if (!cpu_is_xlp9xx()) - status = (status >> (link * XLP_MSIXVEC_PER_LINK)) & - ((1 << XLP_MSIXVEC_PER_LINK) - 1); - - while (status) { - i = __ffs(status); - do_IRQ(irqbase + i); - status &= status - 1; - } - /* Ack at eirr and PIC */ - ack_c0_eirr(PIC_PCIE_MSIX_IRQ(link)); -} diff --git a/arch/mips/pci/pci-xlp.c b/arch/mips/pci/pci-xlp.c deleted file mode 100644 index 9eff9137f78e..000000000000 --- a/arch/mips/pci/pci-xlp.c +++ /dev/null @@ -1,332 +0,0 @@ -/* - * Copyright (c) 2003-2012 Broadcom Corporation - * All Rights Reserved - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the Broadcom - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/msi.h> -#include <linux/mm.h> -#include <linux/irq.h> -#include <linux/irqdesc.h> -#include <linux/console.h> - -#include <asm/io.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> -#include <asm/netlogic/mips-extns.h> - -#include <asm/netlogic/xlp-hal/iomap.h> -#include <asm/netlogic/xlp-hal/xlp.h> -#include <asm/netlogic/xlp-hal/pic.h> -#include <asm/netlogic/xlp-hal/pcibus.h> -#include <asm/netlogic/xlp-hal/bridge.h> - -static void *pci_config_base; - -#define pci_cfg_addr(bus, devfn, off) (((bus) << 20) | ((devfn) << 12) | (off)) - -/* PCI ops */ -static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, - int where) -{ - u32 data; - u32 *cfgaddr; - - where &= ~3; - if (cpu_is_xlp9xx()) { - /* be very careful on SoC buses */ - if (bus->number == 0) { - /* Scan only existing nodes - uboot bug? */ - if (PCI_SLOT(devfn) != 0 || - !nlm_node_present(PCI_FUNC(devfn))) - return 0xffffffff; - } else if (bus->parent->number == 0) { /* SoC bus */ - if (PCI_SLOT(devfn) == 0) /* b.0.0 hangs */ - return 0xffffffff; - if (devfn == 44) /* b.5.4 hangs */ - return 0xffffffff; - } - } else if (bus->number == 0 && PCI_SLOT(devfn) == 1 && where == 0x954) { - return 0xffffffff; - } - cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where)); - data = *cfgaddr; - return data; -} - -static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, - int where, u32 data) -{ - u32 *cfgaddr; - - cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where & ~3)); - *cfgaddr = data; -} - -static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 data; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - data = pci_cfg_read_32bit(bus, devfn, where); - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - - -static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - data = pci_cfg_read_32bit(bus, devfn, where); - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else - data = val; - - pci_cfg_write_32bit(bus, devfn, where, data); - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops nlm_pci_ops = { - .read = nlm_pcibios_read, - .write = nlm_pcibios_write -}; - -static struct resource nlm_pci_mem_resource = { - .name = "XLP PCI MEM", - .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ - .end = 0xdfffffffUL, - .flags = IORESOURCE_MEM, -}; - -static struct resource nlm_pci_io_resource = { - .name = "XLP IO MEM", - .start = 0x14000000UL, /* 64MB PCI IO @ 0x1000_0000 */ - .end = 0x17ffffffUL, - .flags = IORESOURCE_IO, -}; - -struct pci_controller nlm_pci_controller = { - .index = 0, - .pci_ops = &nlm_pci_ops, - .mem_resource = &nlm_pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_resource = &nlm_pci_io_resource, - .io_offset = 0x00000000UL, -}; - -struct pci_dev *xlp_get_pcie_link(const struct pci_dev *dev) -{ - struct pci_bus *bus, *p; - - bus = dev->bus; - - if (cpu_is_xlp9xx()) { - /* find bus with grand parent number == 0 */ - for (p = bus->parent; p && p->parent && p->parent->number != 0; - p = p->parent) - bus = p; - return (p && p->parent) ? bus->self : NULL; - } else { - /* Find the bridge on bus 0 */ - for (p = bus->parent; p && p->number != 0; p = p->parent) - bus = p; - - return p ? bus->self : NULL; - } -} - -int xlp_socdev_to_node(const struct pci_dev *lnkdev) -{ - if (cpu_is_xlp9xx()) - return PCI_FUNC(lnkdev->bus->self->devfn); - else - return PCI_SLOT(lnkdev->devfn) / 8; -} - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - struct pci_dev *lnkdev; - int lnkfunc, node; - - /* - * For XLP PCIe, there is an IRQ per Link, find out which - * link the device is on to assign interrupts - */ - lnkdev = xlp_get_pcie_link(dev); - if (lnkdev == NULL) - return 0; - - lnkfunc = PCI_FUNC(lnkdev->devfn); - node = xlp_socdev_to_node(lnkdev); - - return nlm_irq_to_xirq(node, PIC_PCIE_LINK_LEGACY_IRQ(lnkfunc)); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -/* - * If big-endian, enable hardware byteswap on the PCIe bridges. - * This will make both the SoC and PCIe devices behave consistently with - * readl/writel. - */ -#ifdef __BIG_ENDIAN -static void xlp_config_pci_bswap(int node, int link) -{ - uint64_t nbubase, lnkbase; - u32 reg; - - nbubase = nlm_get_bridge_regbase(node); - lnkbase = nlm_get_pcie_base(node, link); - - /* - * Enable byte swap in hardware. Program each link's PCIe SWAP regions - * from the link's address ranges. - */ - if (cpu_is_xlp9xx()) { - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_9XX_PCIEMEM_BASE0 + link); - nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_MEM_BASE, reg); - - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_9XX_PCIEMEM_LIMIT0 + link); - nlm_write_pci_reg(lnkbase, - PCIE_9XX_BYTE_SWAP_MEM_LIM, reg | 0xfff); - - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_9XX_PCIEIO_BASE0 + link); - nlm_write_pci_reg(lnkbase, PCIE_9XX_BYTE_SWAP_IO_BASE, reg); - - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_9XX_PCIEIO_LIMIT0 + link); - nlm_write_pci_reg(lnkbase, - PCIE_9XX_BYTE_SWAP_IO_LIM, reg | 0xfff); - } else { - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEMEM_BASE0 + link); - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_BASE, reg); - - reg = nlm_read_bridge_reg(nbubase, - BRIDGE_PCIEMEM_LIMIT0 + link); - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_MEM_LIM, reg | 0xfff); - - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_BASE0 + link); - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_BASE, reg); - - reg = nlm_read_bridge_reg(nbubase, BRIDGE_PCIEIO_LIMIT0 + link); - nlm_write_pci_reg(lnkbase, PCIE_BYTE_SWAP_IO_LIM, reg | 0xfff); - } -} -#else -/* Swap configuration not needed in little-endian mode */ -static inline void xlp_config_pci_bswap(int node, int link) {} -#endif /* __BIG_ENDIAN */ - -static int __init pcibios_init(void) -{ - uint64_t pciebase; - int link, n; - u32 reg; - - /* Firmware assigns PCI resources */ - pci_set_flags(PCI_PROBE_ONLY); - pci_config_base = ioremap(XLP_DEFAULT_PCI_ECFG_BASE, 64 << 20); - - /* Extend IO port for memory mapped io */ - ioport_resource.start = 0; - ioport_resource.end = ~0; - - for (n = 0; n < NLM_NR_NODES; n++) { - if (!nlm_node_present(n)) - continue; - - for (link = 0; link < PCIE_NLINKS; link++) { - pciebase = nlm_get_pcie_base(n, link); - if (nlm_read_pci_reg(pciebase, 0) == 0xffffffff) - continue; - xlp_config_pci_bswap(n, link); - xlp_init_node_msi_irqs(n, link); - - /* put in intpin and irq - u-boot does not */ - reg = nlm_read_pci_reg(pciebase, 0xf); - reg &= ~0x1ffu; - reg |= (1 << 8) | PIC_PCIE_LINK_LEGACY_IRQ(link); - nlm_write_pci_reg(pciebase, 0xf, reg); - pr_info("XLP PCIe: Link %d-%d initialized.\n", n, link); - } - } - - set_io_port_base(CKSEG1); - nlm_pci_controller.io_map_base = CKSEG1; - - register_pci_controller(&nlm_pci_controller); - pr_info("XLP PCIe Controller %pR%pR.\n", &nlm_pci_io_resource, - &nlm_pci_mem_resource); - - return 0; -} -arch_initcall(pcibios_init); diff --git a/arch/mips/pci/pci-xlr.c b/arch/mips/pci/pci-xlr.c deleted file mode 100644 index 2a1c81a129ba..000000000000 --- a/arch/mips/pci/pci-xlr.c +++ /dev/null @@ -1,368 +0,0 @@ -/* - * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights - * reserved. - * - * This software is available to you under a choice of one of two - * licenses. You may choose to be licensed under the terms of the GNU - * General Public License (GPL) Version 2, available from the file - * COPYING in the main directory of this source tree, or the NetLogic - * license below: - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * - * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR - * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR - * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, - * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE - * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN - * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include <linux/types.h> -#include <linux/pci.h> -#include <linux/kernel.h> -#include <linux/init.h> -#include <linux/msi.h> -#include <linux/mm.h> -#include <linux/irq.h> -#include <linux/irqdesc.h> -#include <linux/console.h> -#include <linux/pci_regs.h> - -#include <asm/io.h> - -#include <asm/netlogic/interrupt.h> -#include <asm/netlogic/haldefs.h> -#include <asm/netlogic/common.h> - -#include <asm/netlogic/xlr/msidef.h> -#include <asm/netlogic/xlr/iomap.h> -#include <asm/netlogic/xlr/pic.h> -#include <asm/netlogic/xlr/xlr.h> - -static void *pci_config_base; - -#define pci_cfg_addr(bus, devfn, off) (((bus) << 16) | ((devfn) << 8) | (off)) - -/* PCI ops */ -static inline u32 pci_cfg_read_32bit(struct pci_bus *bus, unsigned int devfn, - int where) -{ - u32 data; - u32 *cfgaddr; - - cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where & ~3)); - data = *cfgaddr; - return cpu_to_le32(data); -} - -static inline void pci_cfg_write_32bit(struct pci_bus *bus, unsigned int devfn, - int where, u32 data) -{ - u32 *cfgaddr; - - cfgaddr = (u32 *)(pci_config_base + - pci_cfg_addr(bus->number, devfn, where & ~3)); - *cfgaddr = cpu_to_le32(data); -} - -static int nlm_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 data; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - data = pci_cfg_read_32bit(bus, devfn, where); - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - - -static int nlm_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - data = pci_cfg_read_32bit(bus, devfn, where); - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else - data = val; - - pci_cfg_write_32bit(bus, devfn, where, data); - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops nlm_pci_ops = { - .read = nlm_pcibios_read, - .write = nlm_pcibios_write -}; - -static struct resource nlm_pci_mem_resource = { - .name = "XLR PCI MEM", - .start = 0xd0000000UL, /* 256MB PCI mem @ 0xd000_0000 */ - .end = 0xdfffffffUL, - .flags = IORESOURCE_MEM, -}; - -static struct resource nlm_pci_io_resource = { - .name = "XLR IO MEM", - .start = 0x10000000UL, /* 16MB PCI IO @ 0x1000_0000 */ - .end = 0x100fffffUL, - .flags = IORESOURCE_IO, -}; - -struct pci_controller nlm_pci_controller = { - .index = 0, - .pci_ops = &nlm_pci_ops, - .mem_resource = &nlm_pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_resource = &nlm_pci_io_resource, - .io_offset = 0x00000000UL, -}; - -/* - * The top level PCIe links on the XLS PCIe controller appear as - * bridges. Given a device, this function finds which link it is - * on. - */ -static struct pci_dev *xls_get_pcie_link(const struct pci_dev *dev) -{ - struct pci_bus *bus, *p; - - /* Find the bridge on bus 0 */ - bus = dev->bus; - for (p = bus->parent; p && p->number != 0; p = p->parent) - bus = p; - - return p ? bus->self : NULL; -} - -static int nlm_pci_link_to_irq(int link) -{ - switch (link) { - case 0: - return PIC_PCIE_LINK0_IRQ; - case 1: - return PIC_PCIE_LINK1_IRQ; - case 2: - if (nlm_chip_is_xls_b()) - return PIC_PCIE_XLSB0_LINK2_IRQ; - else - return PIC_PCIE_LINK2_IRQ; - case 3: - if (nlm_chip_is_xls_b()) - return PIC_PCIE_XLSB0_LINK3_IRQ; - else - return PIC_PCIE_LINK3_IRQ; - } - WARN(1, "Unexpected link %d\n", link); - return 0; -} - -static int get_irq_vector(const struct pci_dev *dev) -{ - struct pci_dev *lnk; - int link; - - if (!nlm_chip_is_xls()) - return PIC_PCIX_IRQ; /* for XLR just one IRQ */ - - lnk = xls_get_pcie_link(dev); - if (lnk == NULL) - return 0; - - link = PCI_SLOT(lnk->devfn); - return nlm_pci_link_to_irq(link); -} - -#ifdef CONFIG_PCI_MSI -void arch_teardown_msi_irq(unsigned int irq) -{ -} - -int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc) -{ - struct msi_msg msg; - struct pci_dev *lnk; - int irq, ret; - u16 val; - - /* MSI not supported on XLR */ - if (!nlm_chip_is_xls()) - return 1; - - /* - * Enable MSI on the XLS PCIe controller bridge which was disabled - * at enumeration, the bridge MSI capability is at 0x50 - */ - lnk = xls_get_pcie_link(dev); - if (lnk == NULL) - return 1; - - pci_read_config_word(lnk, 0x50 + PCI_MSI_FLAGS, &val); - if ((val & PCI_MSI_FLAGS_ENABLE) == 0) { - val |= PCI_MSI_FLAGS_ENABLE; - pci_write_config_word(lnk, 0x50 + PCI_MSI_FLAGS, val); - } - - irq = get_irq_vector(dev); - if (irq <= 0) - return 1; - - msg.address_hi = MSI_ADDR_BASE_HI; - msg.address_lo = MSI_ADDR_BASE_LO | - MSI_ADDR_DEST_MODE_PHYSICAL | - MSI_ADDR_REDIRECTION_CPU; - - msg.data = MSI_DATA_TRIGGER_EDGE | - MSI_DATA_LEVEL_ASSERT | - MSI_DATA_DELIVERY_FIXED; - - ret = irq_set_msi_desc(irq, desc); - if (ret < 0) - return ret; - - pci_write_msi_msg(irq, &msg); - return 0; -} -#endif - -/* Extra ACK needed for XLR on chip PCI controller */ -static void xlr_pci_ack(struct irq_data *d) -{ - uint64_t pcibase = nlm_mmio_base(NETLOGIC_IO_PCIX_OFFSET); - - nlm_read_reg(pcibase, (0x140 >> 2)); -} - -/* Extra ACK needed for XLS on chip PCIe controller */ -static void xls_pcie_ack(struct irq_data *d) -{ - uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET); - - switch (d->irq) { - case PIC_PCIE_LINK0_IRQ: - nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); - break; - case PIC_PCIE_LINK1_IRQ: - nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); - break; - case PIC_PCIE_LINK2_IRQ: - nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); - break; - case PIC_PCIE_LINK3_IRQ: - nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); - break; - } -} - -/* For XLS B silicon, the 3,4 PCI interrupts are different */ -static void xls_pcie_ack_b(struct irq_data *d) -{ - uint64_t pciebase_le = nlm_mmio_base(NETLOGIC_IO_PCIE_1_OFFSET); - - switch (d->irq) { - case PIC_PCIE_LINK0_IRQ: - nlm_write_reg(pciebase_le, (0x90 >> 2), 0xffffffff); - break; - case PIC_PCIE_LINK1_IRQ: - nlm_write_reg(pciebase_le, (0x94 >> 2), 0xffffffff); - break; - case PIC_PCIE_XLSB0_LINK2_IRQ: - nlm_write_reg(pciebase_le, (0x190 >> 2), 0xffffffff); - break; - case PIC_PCIE_XLSB0_LINK3_IRQ: - nlm_write_reg(pciebase_le, (0x194 >> 2), 0xffffffff); - break; - } -} - -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - return get_irq_vector(dev); -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -static int __init pcibios_init(void) -{ - void (*extra_ack)(struct irq_data *); - int link, irq; - - /* PSB assigns PCI resources */ - pci_set_flags(PCI_PROBE_ONLY); - pci_config_base = ioremap(DEFAULT_PCI_CONFIG_BASE, 16 << 20); - - /* Extend IO port for memory mapped io */ - ioport_resource.start = 0; - ioport_resource.end = ~0; - - set_io_port_base(CKSEG1); - nlm_pci_controller.io_map_base = CKSEG1; - - pr_info("Registering XLR/XLS PCIX/PCIE Controller.\n"); - register_pci_controller(&nlm_pci_controller); - - /* - * For PCI interrupts, we need to ack the PCI controller too, overload - * irq handler data to do this - */ - if (!nlm_chip_is_xls()) { - /* XLR PCI controller ACK */ - nlm_set_pic_extra_ack(0, PIC_PCIX_IRQ, xlr_pci_ack); - } else { - if (nlm_chip_is_xls_b()) - extra_ack = xls_pcie_ack_b; - else - extra_ack = xls_pcie_ack; - for (link = 0; link < 4; link++) { - irq = nlm_pci_link_to_irq(link); - nlm_set_pic_extra_ack(0, irq, extra_ack); - } - } - return 0; -} - -arch_initcall(pcibios_init); |