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| author | Stafford Horne <shorne@gmail.com> | 2023-04-14 10:25:58 +0300 |
|---|---|---|
| committer | Stafford Horne <shorne@gmail.com> | 2023-04-26 17:08:06 +0300 |
| commit | 63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf (patch) | |
| tree | b547d7264d6e02178c8e755168edb0d17702f760 /arch/openrisc/include/asm | |
| parent | 812489ac4dd91144a74ce65ecf232252a2e406fb (diff) | |
| download | linux-63d7f9f11e5e81de2ce8f1c7a8aaed5b0288eddf.tar.xz | |
openrisc: Support storing and restoring fpu state
OpenRISC floating point state is not so expensive to save as OpenRISC uses
general purpose registers for floating point instructions. We need to save
only the floating point status and control register, FPCSR.
Add support to maintain the FPCSR unconditionally upon exceptions and
switches. On machines that do not support FPU this will always just
store 0x0 and restore is a no-op. On FPU systems this adds an
additional special purpose register read/write and read/write to memory
(already cached).
Signed-off-by: Stafford Horne <shorne@gmail.com>
Diffstat (limited to 'arch/openrisc/include/asm')
| -rw-r--r-- | arch/openrisc/include/asm/ptrace.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/openrisc/include/asm/ptrace.h b/arch/openrisc/include/asm/ptrace.h index 01f81d4e97dc..375147ff71fc 100644 --- a/arch/openrisc/include/asm/ptrace.h +++ b/arch/openrisc/include/asm/ptrace.h @@ -59,7 +59,7 @@ struct pt_regs { * -1 for all other exceptions. */ long orig_gpr11; /* For restarting system calls */ - long dummy; /* Cheap alignment fix */ + long fpcsr; /* Floating point control status register. */ long dummy2; /* Cheap alignment fix */ }; @@ -115,6 +115,6 @@ static inline long regs_return_value(struct pt_regs *regs) #define PT_GPR31 124 #define PT_PC 128 #define PT_ORIG_GPR11 132 -#define PT_SYSCALLNO 136 +#define PT_FPCSR 136 #endif /* __ASM_OPENRISC_PTRACE_H */ |