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author | Michael Ellerman <mpe@ellerman.id.au> | 2021-10-14 05:44:24 +0300 |
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committer | Michael Ellerman <mpe@ellerman.id.au> | 2021-10-28 14:29:25 +0300 |
commit | fef071be57dc43679a32d5b0e6ee176d6f12e9f2 (patch) | |
tree | f2a5c4b1a3cce9b367d793eac19b1ff3f8a0daa2 /arch/parisc | |
parent | 3c12b4df8d5e026345a19886ae375b3ebc33c0b6 (diff) | |
download | linux-fef071be57dc43679a32d5b0e6ee176d6f12e9f2.tar.xz |
powerpc/dcr: Use cmplwi instead of 3-argument cmpli
In dcr-low.S we use cmpli with three arguments, instead of four
arguments as defined in the ISA:
cmpli cr0,r3,1024
This appears to be a PPC440-ism, looking at the "PPC440x5 CPU Core
User’s Manual" it shows cmpli having no L field, but implied to be 0 due
to the core being 32-bit. It mentions that the ISA defines four
arguments and recommends using cmplwi.
It also corresponds to the old POWER instruction set, which had no L
field there, a reserved bit instead.
dcr-low.S is only built 32-bit, because it is only built when
DCR_NATIVE=y, which is only selected by 40x and 44x. Looking at the
generated code (with gcc/gas) we see cmplwi as expected.
Although gas is happy with the 3-argument version when building for
32-bit, the LLVM assembler is not and errors out with:
arch/powerpc/sysdev/dcr-low.S:27:10: error: invalid operand for instruction
cmpli 0,%r3,1024; ...
^
Switch to the cmplwi extended opcode, which avoids any confusion when
reading the ISA, fixes the issue with the LLVM assembler, and also means
the code could be built 64-bit in future (though that's very unlikely).
Reported-by: Nick Desaulniers <ndesaulniers@google.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
BugLink: https://github.com/ClangBuiltLinux/linux/issues/1419
Link: https://lore.kernel.org/r/20211014024424.528848-1-mpe@ellerman.id.au
Diffstat (limited to 'arch/parisc')
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