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| author | Benjamin Gray <bgray@linux.ibm.com> | 2023-06-19 10:36:25 +0300 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2023-06-19 10:36:26 +0300 |
| commit | 5bcba4e6c13f0c889da1f9e67ee10accd9ca4c19 (patch) | |
| tree | da6844eb74b2f2a374adf652893f3b6b56f5e952 /arch/powerpc/include/asm/ppc-opcode.h | |
| parent | 0ffd60b782ed79349baf28dd3259c872f39274e9 (diff) | |
| download | linux-5bcba4e6c13f0c889da1f9e67ee10accd9ca4c19.tar.xz | |
powerpc/dexcr: Handle hashchk exception
Recognise and pass the appropriate signal to the user program when a
hashchk instruction triggers. This is independent of allowing
configuration of DEXCR[NPHIE], as a hypervisor can enforce this aspect
regardless of the kernel.
The signal mirrors how ARM reports their similar check failure. For
example, their FPAC handler in arch/arm64/kernel/traps.c do_el0_fpac()
does this. When we fail to read the instruction that caused the fault
we send a segfault, similar to how emulate_math() does it.
Signed-off-by: Benjamin Gray <bgray@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://msgid.link/20230616034846.311705-5-bgray@linux.ibm.com
Diffstat (limited to 'arch/powerpc/include/asm/ppc-opcode.h')
| -rw-r--r-- | arch/powerpc/include/asm/ppc-opcode.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h index ca5a0da7df4e..ef6972aa33b9 100644 --- a/arch/powerpc/include/asm/ppc-opcode.h +++ b/arch/powerpc/include/asm/ppc-opcode.h @@ -222,6 +222,7 @@ #define OP_31_XOP_STFSX 663 #define OP_31_XOP_STFSUX 695 #define OP_31_XOP_STFDX 727 +#define OP_31_XOP_HASHCHK 754 #define OP_31_XOP_STFDUX 759 #define OP_31_XOP_LHBRX 790 #define OP_31_XOP_LFIWAX 855 |