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authorJiri Kosina <jkosina@suse.cz>2023-11-01 02:07:35 +0300
committerJiri Kosina <jkosina@suse.cz>2023-11-01 02:07:35 +0300
commit20cd569d7ee8fce24e8753f0f43af6c420557b1f (patch)
treef559cfda594846795aa51c99d96f92d8c912851a /arch/riscv/Kconfig.errata
parent62cc9c3cb3ec1bf31cc116146185ed97b450836a (diff)
parenteeebfe6259ba2d5b0980eb7b0df384eb77e9e4f5 (diff)
downloadlinux-20cd569d7ee8fce24e8753f0f43af6c420557b1f.tar.xz
Merge branch 'for-6.7/config_pm' into for-linus
- #ifdef CONFIG_PM removal from HID code (Thomas Weißschuh)
Diffstat (limited to 'arch/riscv/Kconfig.errata')
-rw-r--r--arch/riscv/Kconfig.errata21
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index 0c8f4652cd82..566bcefeab50 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -1,5 +1,26 @@
menu "CPU errata selection"
+config ERRATA_ANDES
+ bool "Andes AX45MP errata"
+ depends on RISCV_ALTERNATIVE && RISCV_SBI
+ help
+ All Andes errata Kconfig depend on this Kconfig. Disabling
+ this Kconfig will disable all Andes errata. Please say "Y"
+ here if your platform uses Andes CPU cores.
+
+ Otherwise, please say "N" here to avoid unnecessary overhead.
+
+config ERRATA_ANDES_CMO
+ bool "Apply Andes cache management errata"
+ depends on ERRATA_ANDES && ARCH_R9A07G043
+ select RISCV_DMA_NONCOHERENT
+ default y
+ help
+ This will apply the cache management errata to handle the
+ non-standard handling on non-coherent operations on Andes cores.
+
+ If you don't know what to do here, say "Y".
+
config ERRATA_SIFIVE
bool "SiFive errata"
depends on RISCV_ALTERNATIVE