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authorAlexandre Ghiti <alexandre.ghiti@canonical.com>2021-12-06 13:46:51 +0300
committerPalmer Dabbelt <palmer@rivosinc.com>2022-01-20 04:54:09 +0300
commite8a62cc26ddf53a3c6ba2a8d33036cf7b84f3923 (patch)
tree15b9020880a651c756268a4560b8c6c720fc1031 /arch/riscv/Kconfig
parent60639f74c2f4fcc3ffa2ac0b120eaa874ccc713f (diff)
downloadlinux-e8a62cc26ddf53a3c6ba2a8d33036cf7b84f3923.tar.xz
riscv: Implement sv48 support
By adding a new 4th level of page table, give the possibility to 64bit kernel to address 2^48 bytes of virtual address: in practice, that offers 128TB of virtual address space to userspace and allows up to 64TB of physical memory. If the underlying hardware does not support sv48, we will automatically fallback to a standard 3-level page table by folding the new PUD level into PGDIR level. In order to detect HW capabilities at runtime, we use SATP feature that ignores writes with an unsupported mode. Signed-off-by: Alexandre Ghiti <alexandre.ghiti@canonical.com> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/Kconfig')
-rw-r--r--arch/riscv/Kconfig4
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 7945bacb1d0e..c4289d755dd4 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -150,7 +150,7 @@ config PAGE_OFFSET
hex
default 0xC0000000 if 32BIT
default 0x80000000 if 64BIT && !MMU
- default 0xffffffd800000000 if 64BIT
+ default 0xffffaf8000000000 if 64BIT
config KASAN_SHADOW_OFFSET
hex
@@ -201,7 +201,7 @@ config FIX_EARLYCON_MEM
config PGTABLE_LEVELS
int
- default 3 if 64BIT
+ default 4 if 64BIT
default 2
config LOCKDEP_SUPPORT