summaryrefslogtreecommitdiff
path: root/arch/riscv/boot/dts/microchip/mpfs.dtsi
diff options
context:
space:
mode:
authorConor Dooley <conor.dooley@microchip.com>2023-11-26 14:40:54 +0300
committerConor Dooley <conor.dooley@microchip.com>2023-11-26 14:44:51 +0300
commit79997eda0d31bc68203c95ecb978773ee6ce7a1f (patch)
tree466a91a1f60a9737f231b32711226db90d9706a3 /arch/riscv/boot/dts/microchip/mpfs.dtsi
parente80ed63affc9a9b4aacb44180ecd7ed601839599 (diff)
downloadlinux-79997eda0d31bc68203c95ecb978773ee6ce7a1f.tar.xz
riscv: dts: microchip: move timebase-frequency to mpfs.dtsi
The timebase-frequency on PolarFire SoC is not set by an oscillator on the board, but rather by an internal divider, so move the property to mpfs.dtsi. This looks to be copy-pasta from the SiFive Unleashed as the comments in both places were almost identical. In the Unleashed's case this looks to actually be valid, as the clock is provided by a crystal on the PCB. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- CC: Conor Dooley <conor.dooley@microchip.com> CC: Daire McNamara <daire.mcnamara@microchip.com> CC: Rob Herring <robh+dt@kernel.org> CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org> CC: Paul Walmsley <paul.walmsley@sifive.com> CC: Palmer Dabbelt <palmer@dabbelt.com> CC: linux-riscv@lists.infradead.org CC: devicetree@vger.kernel.org
Diffstat (limited to 'arch/riscv/boot/dts/microchip/mpfs.dtsi')
-rw-r--r--arch/riscv/boot/dts/microchip/mpfs.dtsi1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi
index a6faf24f1dba..266489d43912 100644
--- a/arch/riscv/boot/dts/microchip/mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi
@@ -13,6 +13,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ timebase-frequency = <1000000>;
cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";