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| author | Jonas Hahnfeld <hahnjo@hahnjo.de> | 2022-07-05 22:04:32 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-07-15 00:37:00 +0300 |
| commit | ef09fa67dc7dc7d839d8f9bee43ecacc83401de5 (patch) | |
| tree | f6eb04d1a628d68c39170debcc1930702971465a /arch/riscv/boot/dts | |
| parent | f2906aa863381afb0015a9eb7fefad885d4e5a56 (diff) | |
| download | linux-ef09fa67dc7dc7d839d8f9bee43ecacc83401de5.tar.xz | |
riscv: dts: starfive: Add JH7100 CPU topology
Add cpu-map binding to inform the kernel about the hardware topology
of the CPU cores.
Before this change, lstopo would report 1 core with 2 threads:
Machine (7231MB total)
Package L#0
NUMANode L#0 (P#0 7231MB)
L2 L#0 (2048KB) + Core L#0
L1d L#0 (32KB) + L1i L#0 (32KB) + PU L#0 (P#0)
L1d L#1 (32KB) + L1i L#1 (32KB) + PU L#1 (P#1)
After this change, it correctly identifies two cores:
Machine (7231MB total)
Package L#0
NUMANode L#0 (P#0 7231MB)
L2 L#0 (2048KB)
L1d L#0 (32KB) + L1i L#0 (32KB) + Core L#0 + PU L#0 (P#0)
L1d L#1 (32KB) + L1i L#1 (32KB) + Core L#1 + PU L#1 (P#1)
Signed-off-by: Jonas Hahnfeld <hahnjo@hahnjo.de>
Co-developed-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20220705190435.1790466-2-mail@conchuod.ie
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/boot/dts')
| -rw-r--r-- | arch/riscv/boot/dts/starfive/jh7100.dtsi | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 69f22f9aad9d..c617a61e26e2 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -17,7 +17,7 @@ #address-cells = <1>; #size-cells = <0>; - cpu@0 { + U74_0: cpu@0 { compatible = "sifive,u74-mc", "riscv"; reg = <0>; d-cache-block-size = <64>; @@ -42,7 +42,7 @@ }; }; - cpu@1 { + U74_1: cpu@1 { compatible = "sifive,u74-mc", "riscv"; reg = <1>; d-cache-block-size = <64>; @@ -66,6 +66,18 @@ #interrupt-cells = <1>; }; }; + + cpu-map { + cluster0 { + core0 { + cpu = <&U74_0>; + }; + + core1 { + cpu = <&U74_1>; + }; + }; + }; }; osc_sys: osc_sys { |