diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2022-05-11 22:29:21 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-05-12 07:36:33 +0300 |
| commit | a35707c3d850dda0ceefb75b1b3bd191921d5765 (patch) | |
| tree | 00188dae0c8c04eabd08b304924d1d84c92acbd1 /arch/riscv/errata/sifive/errata.c | |
| parent | 1745cfafebdfb017f6871c80f9894910a76373a4 (diff) | |
| download | linux-a35707c3d850dda0ceefb75b1b3bd191921d5765.tar.xz | |
riscv: add memory-type errata for T-Head
Some current cpus based on T-Head cores implement memory-types
way different than described in the svpbmt spec even going
so far as using PTE bits marked as reserved.
Add the T-Head vendor-id and necessary errata code to
replace the affected instructions.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220511192921.2223629-13-heiko@sntech.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/errata/sifive/errata.c')
| -rw-r--r-- | arch/riscv/errata/sifive/errata.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c index 3e39587a49dc..672f02b21ce0 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -88,10 +88,15 @@ void __init_or_module sifive_errata_patch_func(struct alt_entry *begin, unsigned int stage) { struct alt_entry *alt; - u32 cpu_req_errata = sifive_errata_probe(archid, impid); + u32 cpu_req_errata; u32 cpu_apply_errata = 0; u32 tmp; + if (stage == RISCV_ALTERNATIVES_EARLY_BOOT) + return; + + cpu_req_errata = sifive_errata_probe(archid, impid); + for (alt = begin; alt < end; alt++) { if (alt->vendor_id != SIFIVE_VENDOR_ID) continue; |