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| author | Samuel Holland <samuel.holland@sifive.com> | 2024-03-27 07:49:49 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-04-29 20:49:31 +0300 |
| commit | d6dcdabafcd7c612b164079d00da6d9775863a0b (patch) | |
| tree | 891257d2841136d48575cc49123a13f10974beb3 /arch/riscv/errata | |
| parent | 20e03d702e00a3e0269a1d6f9549c2e370492054 (diff) | |
| download | linux-d6dcdabafcd7c612b164079d00da6d9775863a0b.tar.xz | |
riscv: Avoid TLB flush loops when affected by SiFive CIP-1200
Implementations affected by SiFive errata CIP-1200 have a bug which
forces the kernel to always use the global variant of the sfence.vma
instruction. When affected by this errata, do not attempt to flush a
range of addresses; each iteration of the loop would actually flush the
whole TLB instead. Instead, minimize the overall number of sfence.vma
instructions.
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Yunhui Cui <cuiyunhui@bytedance.com>
Link: https://lore.kernel.org/r/20240327045035.368512-9-samuel.holland@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/errata')
| -rw-r--r-- | arch/riscv/errata/sifive/errata.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/riscv/errata/sifive/errata.c b/arch/riscv/errata/sifive/errata.c index 3d9a32d791f7..716cfedad3a2 100644 --- a/arch/riscv/errata/sifive/errata.c +++ b/arch/riscv/errata/sifive/errata.c @@ -42,6 +42,11 @@ static bool errata_cip_1200_check_func(unsigned long arch_id, unsigned long imp return false; if ((impid & 0xffffff) > 0x200630 || impid == 0x1200626) return false; + +#ifdef CONFIG_MMU + tlb_flush_all_threshold = 0; +#endif + return true; } |