diff options
| author | Andrew Jones <ajones@ventanamicro.com> | 2022-10-02 07:48:14 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-10-02 07:48:14 +0300 |
| commit | bb233a11dc6b3774fd46087242d7627ecf5293ed (patch) | |
| tree | 3546f16c889713961621f4285b242f19a782f2ac /arch/riscv/include/asm | |
| parent | 5ac43ab2e3fe4e5d48ef313a99d0591021c3bbdd (diff) | |
| download | linux-bb233a11dc6b3774fd46087242d7627ecf5293ed.tar.xz | |
riscv: KVM: Apply insn-def to hfence encodings
Introduce hfence instruction encodings and apply them to KVM's use.
With the self-documenting nature of the instruction encoding macros,
and a spec always within arm's reach, it's safe to remove the
comments, so we do that too.
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/include/asm')
| -rw-r--r-- | arch/riscv/include/asm/insn-def.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/riscv/include/asm/insn-def.h b/arch/riscv/include/asm/insn-def.h index 635612e59b25..c8aca3c27433 100644 --- a/arch/riscv/include/asm/insn-def.h +++ b/arch/riscv/include/asm/insn-def.h @@ -87,4 +87,14 @@ #define RV___RS1(v) __RV_REG(v) #define RV___RS2(v) __RV_REG(v) +#define RV_OPCODE_SYSTEM RV_OPCODE(115) + +#define HFENCE_VVMA(vaddr, asid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(17), \ + __RD(0), RS1(vaddr), RS2(asid)) + +#define HFENCE_GVMA(gaddr, vmid) \ + INSN_R(OPCODE_SYSTEM, FUNC3(0), FUNC7(49), \ + __RD(0), RS1(gaddr), RS2(vmid)) + #endif /* __ASM_INSN_DEF_H */ |