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| author | Andy Chiu <andy.chiu@sifive.com> | 2024-01-15 08:59:27 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-01-16 18:14:00 +0300 |
| commit | 5b6048f2ff710196c85ce14373febe8be5115bbe (patch) | |
| tree | 5f618b35a76dd50561a6bec9f82c548ba0f344c5 /arch/riscv/include | |
| parent | d6c78f1ca3e8ec3fd1afa1bc567cdf083e7af9fe (diff) | |
| download | linux-5b6048f2ff710196c85ce14373febe8be5115bbe.tar.xz | |
riscv: vector: use a mask to write vstate_ctrl
riscv_v_ctrl_set() should only touch bits within
PR_RISCV_V_VSTATE_CTRL_MASK. So, use the mask when we really set task's
vstate_ctrl.
Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Tested-by: Björn Töpel <bjorn@rivosinc.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240115055929.4736-9-andy.chiu@sifive.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include')
0 files changed, 0 insertions, 0 deletions