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| author | Anup Patel <anup.patel@wdc.com> | 2021-11-26 14:35:51 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2022-01-06 12:46:58 +0300 |
| commit | a457fd5660efa9cf960d2461156a1025bfdb13fa (patch) | |
| tree | 74381143d7ad54e9dd3238f35cc79257070a355d /arch/riscv/kvm | |
| parent | ef8949a986f0e325b1d535389101541849d611d3 (diff) | |
| download | linux-a457fd5660efa9cf960d2461156a1025bfdb13fa.tar.xz | |
RISC-V: KVM: Add VM capability to allow userspace get GPA bits
The number of GPA bits supported for a RISC-V Guest/VM is based on the
MMU mode used by the G-stage translation. The KVM RISC-V will detect and
use the best possible MMU mode for the G-stage in kvm_arch_init().
We add a generic VM capability KVM_CAP_VM_GPA_BITS which can be used by
the KVM userspace to get the number of GPA (guest physical address) bits
supported for a Guest/VM.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-and-tested-by: Atish Patra <atishp@rivosinc.com>
Diffstat (limited to 'arch/riscv/kvm')
| -rw-r--r-- | arch/riscv/kvm/mmu.c | 5 | ||||
| -rw-r--r-- | arch/riscv/kvm/vm.c | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/riscv/kvm/mmu.c b/arch/riscv/kvm/mmu.c index 5f2736c2e773..9af67dbdc66a 100644 --- a/arch/riscv/kvm/mmu.c +++ b/arch/riscv/kvm/mmu.c @@ -769,3 +769,8 @@ unsigned long kvm_riscv_stage2_mode(void) { return stage2_mode >> HGATP_MODE_SHIFT; } + +int kvm_riscv_stage2_gpa_bits(void) +{ + return stage2_gpa_bits; +} diff --git a/arch/riscv/kvm/vm.c b/arch/riscv/kvm/vm.c index 7619691d8953..c768f75279ef 100644 --- a/arch/riscv/kvm/vm.c +++ b/arch/riscv/kvm/vm.c @@ -74,6 +74,9 @@ int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext) case KVM_CAP_NR_MEMSLOTS: r = KVM_USER_MEM_SLOTS; break; + case KVM_CAP_VM_GPA_BITS: + r = kvm_riscv_stage2_gpa_bits(); + break; default: r = 0; break; |