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| author | Daniel Henrique Barboza <dbarboza@ventanamicro.com> | 2023-08-03 19:32:58 +0300 |
|---|---|---|
| committer | Anup Patel <anup@brainfault.org> | 2023-08-08 14:55:53 +0300 |
| commit | bea8d23713a2b2dc07ae9d7325b1269dff8c8a1f (patch) | |
| tree | 471445d19c11cc55f5d2386f60cb779423e5df79 /arch/riscv/kvm | |
| parent | d57304bbfb742bf744d2cd4dc3a08ce3fbfba787 (diff) | |
| download | linux-bea8d23713a2b2dc07ae9d7325b1269dff8c8a1f.tar.xz | |
RISC-V: KVM: avoid EBUSY when writing same ISA val
kvm_riscv_vcpu_set_reg_config() will return -EBUSY if the ISA config reg
is being written after the VCPU ran at least once.
The same restriction isn't placed in kvm_riscv_vcpu_get_reg_config(), so
there's a chance that we'll -EBUSY out on an ISA config reg write even
if the userspace intended no changes to it.
We'll allow the same form of 'lazy writing' that registers such as
zicbom/zicboz_block_size supports: avoid erroring out if userspace made
no changes to the ISA config reg.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/kvm')
| -rw-r--r-- | arch/riscv/kvm/vcpu_onereg.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 971a2eb83180..a0b0364b038f 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -190,6 +190,13 @@ static int kvm_riscv_vcpu_set_reg_config(struct kvm_vcpu *vcpu, if (fls(reg_val) >= RISCV_ISA_EXT_BASE) return -EINVAL; + /* + * Return early (i.e. do nothing) if reg_val is the same + * value retrievable via kvm_riscv_vcpu_get_reg_config(). + */ + if (reg_val == (vcpu->arch.isa[0] & KVM_RISCV_BASE_ISA_MASK)) + break; + if (!vcpu->arch.ran_atleast_once) { /* Ignore the enable/disable request for certain extensions */ for (i = 0; i < RISCV_ISA_EXT_BASE; i++) { |