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authorYash Shah <yash.shah@sifive.com>2019-05-06 13:48:40 +0300
committerPalmer Dabbelt <palmer@sifive.com>2019-05-17 06:42:13 +0300
commita967a289f16969527a8a41e261695c639a69bee4 (patch)
treeeda00cc7ecc719a9ed5e9cb82d27b64fb929d4fa /arch/riscv/mm/Makefile
parent5545b6d1ba25ce4a3a339b1edb760e666e693599 (diff)
downloadlinux-a967a289f16969527a8a41e261695c639a69bee4.tar.xz
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs
The driver currently supports only SiFive FU540-C000 platform. The initial version of L2 cache controller driver includes: - Initial configuration reporting at boot up. - Support for ECC related functionality. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'arch/riscv/mm/Makefile')
-rw-r--r--arch/riscv/mm/Makefile1
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/mm/Makefile b/arch/riscv/mm/Makefile
index 0f1295d8731f..8db569141485 100644
--- a/arch/riscv/mm/Makefile
+++ b/arch/riscv/mm/Makefile
@@ -10,3 +10,4 @@ obj-y += extable.o
obj-y += ioremap.o
obj-y += cacheflush.o
obj-y += context.o
+obj-y += sifive_l2_cache.o