diff options
| author | Christoph Hellwig <hch@lst.de> | 2023-10-28 18:51:01 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-11-07 20:37:42 +0300 |
| commit | 946bb33d330251966223f770f64885c79448b1a1 (patch) | |
| tree | 67ac511133dd5b26ed1a8f2a03f77db42b6ca3ab /arch/riscv/mm/cache-ops.c | |
| parent | f367db71d5755d6476dd6f3d84b53c098c111255 (diff) | |
| download | linux-946bb33d330251966223f770f64885c79448b1a1.tar.xz | |
riscv: split cache ops out of dma-noncoherent.c
The cache ops are also used by the pmem code which is unconditionally
built into the kernel. Move them into a separate file that is built
based on the correct config option.
Fixes: fd962781270e ("riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT")
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Tested-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> #
Link: https://lore.kernel.org/r/20231028155101.1039049-1-hch@lst.de
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/mm/cache-ops.c')
| -rw-r--r-- | arch/riscv/mm/cache-ops.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/arch/riscv/mm/cache-ops.c b/arch/riscv/mm/cache-ops.c new file mode 100644 index 000000000000..a993ad11d0ec --- /dev/null +++ b/arch/riscv/mm/cache-ops.c @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + */ + +#include <asm/dma-noncoherent.h> + +struct riscv_nonstd_cache_ops noncoherent_cache_ops __ro_after_init; + +void +riscv_noncoherent_register_cache_ops(const struct riscv_nonstd_cache_ops *ops) +{ + if (!ops) + return; + noncoherent_cache_ops = *ops; +} +EXPORT_SYMBOL_GPL(riscv_noncoherent_register_cache_ops); |