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authorGuo Ren <guoren@linux.alibaba.com>2023-01-27 06:53:06 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2023-02-14 21:11:53 +0300
commit7d151eccd07a0a9767f3e0af976e05a9210ea678 (patch)
tree88018894c0f5c1e4542c9c1458bdc50e93cc0cd0 /arch/riscv/mm/cacheflush.c
parent9f55a0a2d94fd731e396b8586be6babca49dfd92 (diff)
downloadlinux-7d151eccd07a0a9767f3e0af976e05a9210ea678.tar.xz
riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte
commit 950b879b7f0251317d26bae0687e72592d607532 upstream. In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean in __sync_icache_dcache()"), we found RISC-V has the same issue as the previous arm64. The previous implementation didn't guarantee the correct sequence of operations, which means flush_icache_all() hasn't been called when the PG_dcache_clean was set. That would cause a risk of page synchronization. Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable") Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230127035306.1819561-1-guoren@kernel.org Cc: stable@vger.kernel.org Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/riscv/mm/cacheflush.c')
-rw-r--r--arch/riscv/mm/cacheflush.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 57b40a350420..8a2e7040f8fc 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -83,8 +83,10 @@ void flush_icache_pte(pte_t pte)
{
struct page *page = pte_page(pte);
- if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+ if (!test_bit(PG_dcache_clean, &page->flags)) {
flush_icache_all();
+ set_bit(PG_dcache_clean, &page->flags);
+ }
}
#endif /* CONFIG_MMU */