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author | Daniel Sneddon <daniel.sneddon@linux.intel.com> | 2024-03-13 19:47:57 +0300 |
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committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-04-10 17:38:24 +0300 |
commit | aec26bd00ed73c21f8f98b3e1667bc4cf016a9cf (patch) | |
tree | f71a2f23e979ddc40642fdb90a7c80b79014377b /arch/riscv | |
parent | 8f51637712e4da5be410a1666f8aee0d86eef898 (diff) | |
download | linux-aec26bd00ed73c21f8f98b3e1667bc4cf016a9cf.tar.xz |
x86/bhi: Define SPEC_CTRL_BHI_DIS_S
commit 0f4a837615ff925ba62648d280a861adf1582df7 upstream.
Newer processors supports a hardware control BHI_DIS_S to mitigate
Branch History Injection (BHI). Setting BHI_DIS_S protects the kernel
from userspace BHI attacks without having to manually overwrite the
branch history.
Define MSR_SPEC_CTRL bit BHI_DIS_S and its enumeration CPUID.BHI_CTRL.
Mitigation is enabled later.
Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch/riscv')
0 files changed, 0 insertions, 0 deletions