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| author | Yangyu Chen <cyy@cyyself.name> | 2024-01-09 21:48:59 +0300 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-27 17:29:27 +0300 |
| commit | 542124fc0d5cccea273bccf2ee58545ac17aad3f (patch) | |
| tree | 379b39aa329dfbbc4e7f711675719c189c28dd22 /arch/riscv | |
| parent | 84c3a079ab98f729e9a968a201d9aa8d196195a1 (diff) | |
| download | linux-542124fc0d5cccea273bccf2ee58545ac17aad3f.tar.xz | |
RISC-V: only flush icache when it has VM_EXEC set
As I-Cache flush on current RISC-V needs to send IPIs to every CPU cores
in the system is very costly, limiting flush_icache_mm to be called only
when vma->vm_flags has VM_EXEC can help minimize the frequency of these
operations. It improves performance and reduces disturbances when
copy_from_user_page is needed such as profiling with perf.
For I-D coherence concerns, it will not fail if such a page adds VM_EXEC
flags in the future since we have checked it in the __set_pte_at function.
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
Link: https://lore.kernel.org/r/tencent_6D851035F6F2FD0B5A69FB391AE39AC6300A@qq.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv')
| -rw-r--r-- | arch/riscv/include/asm/cacheflush.h | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h index a129dac4521d..dd8d07146116 100644 --- a/arch/riscv/include/asm/cacheflush.h +++ b/arch/riscv/include/asm/cacheflush.h @@ -33,8 +33,11 @@ static inline void flush_dcache_page(struct page *page) * so instead we just flush the whole thing. */ #define flush_icache_range(start, end) flush_icache_all() -#define flush_icache_user_page(vma, pg, addr, len) \ - flush_icache_mm(vma->vm_mm, 0) +#define flush_icache_user_page(vma, pg, addr, len) \ +do { \ + if (vma->vm_flags & VM_EXEC) \ + flush_icache_mm(vma->vm_mm, 0); \ +} while (0) #ifdef CONFIG_64BIT #define flush_cache_vmap(start, end) flush_tlb_kernel_range(start, end) |