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authorArnd Bergmann <arnd@arndb.de>2023-10-17 00:14:09 +0300
committerArnd Bergmann <arnd@arndb.de>2023-10-17 00:14:10 +0300
commite4078ebbddf69f5a82f164dc07d50321b7f641cf (patch)
treefc8c0d24dd990f3462e6b659d5eb9c081468ab70 /arch/riscv
parent5e24617f6686e28e8db246db366abd1eb7953c92 (diff)
parentcf98fe6b579e55aa71b6197e34c112b51f0c2a66 (diff)
downloadlinux-e4078ebbddf69f5a82f164dc07d50321b7f641cf.tar.xz
Merge tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes
RISC-V Devicetrees for v6.6-final A single fix for the Starfive VisionFive 2 platform so that chip select for SPI matches the vendor documentation. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> * tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: riscv: dts: starfive: visionfive 2: correct spi's ss pin Link: https://lore.kernel.org/r/20231015-outmatch-tragedy-228f91d396b5@spud Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/riscv')
-rw-r--r--arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index 12ebe9792356..2c02358abd71 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -431,7 +431,7 @@
};
ss-pins {
- pinmux = <GPIOMUX(48, GPOUT_SYS_SPI0_FSS,
+ pinmux = <GPIOMUX(49, GPOUT_SYS_SPI0_FSS,
GPOEN_ENABLE,
GPI_SYS_SPI0_FSS)>;
bias-disable;