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authorPaul Mundt <lethal@linux-sh.org>2008-11-12 06:53:48 +0300
committerPaul Mundt <lethal@linux-sh.org>2008-11-12 06:53:48 +0300
commit185aed75570fb4f78ef283dfa26cd9da5fa06a91 (patch)
treea98cb3f46bf9426f8d4a660d63b8a3ac7d9f369d /arch/sh/include/asm/io.h
parentade7a9b4ccd20ab8159c77a0abd20552f2d6b06c (diff)
downloadlinux-185aed75570fb4f78ef283dfa26cd9da5fa06a91.tar.xz
sh: Provide a sane valid_phys_addr_range() to prevent TLB reset with PMB.
With the PMB enabled, only P1SEG and up are covered by the PMB mappings, meaning that situations where out-of-bounds physical addresses are read from will lead to TLB reset after the PMB miss, allowing for use cases like dd if=/dev/mem to reset the TLB. Fix this up to make sure the reference is between __MEMORY_START (phys) and __pa(high_memory). This is coherent across all variants of sh/sh64 with and without MMU, though the PMB bug itself is only applicable to SH-4A parts. Reported-by: Hideo Saito <saito@densan.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/asm/io.h')
-rw-r--r--arch/sh/include/asm/io.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sh/include/asm/io.h b/arch/sh/include/asm/io.h
index 436c28539577..65eaae34e753 100644
--- a/arch/sh/include/asm/io.h
+++ b/arch/sh/include/asm/io.h
@@ -293,6 +293,10 @@ __ioremap_mode(unsigned long offset, unsigned long size, unsigned long flags)
*/
#define xlate_dev_kmem_ptr(p) p
+#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
+int valid_phys_addr_range(unsigned long addr, size_t size);
+int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
+
#endif /* __KERNEL__ */
#endif /* __ASM_SH_IO_H */