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authorRich Felker <dalias@libc.org>2016-03-23 01:02:23 +0300
committerRich Felker <dalias@libc.org>2016-07-31 06:33:32 +0300
commit57155c6523074dd937b8feafcfaa98c82218faa6 (patch)
tree4ea86ec76b955599269de0963ed4851406997cfc /arch/sh/mm
parentbbe6c77857c38f4acbdc4fc70399515226d1859a (diff)
downloadlinux-57155c6523074dd937b8feafcfaa98c82218faa6.tar.xz
sh: disable aliased page logic on NOMMU models
SH3/4 (with MMU) have a virtually indexed cache, requiring explicit work to avoid consistency problems arising from having the same physical address range cached in multiple cache lines. This is unneeded for the NOMMU case, and some of the resulting code paths (kmap_coherent) don't work. SH2 only avoided this problem by having a 4-way associative cache with way size equal to the page size (4k), yielding no cache index bits outside of the page offset and thus no aliases. Signed-off-by: Rich Felker <dalias@libc.org>
Diffstat (limited to 'arch/sh/mm')
-rw-r--r--arch/sh/mm/cache.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/sh/mm/cache.c b/arch/sh/mm/cache.c
index e58cfbf45150..776d664a40c5 100644
--- a/arch/sh/mm/cache.c
+++ b/arch/sh/mm/cache.c
@@ -244,7 +244,11 @@ void flush_cache_sigtramp(unsigned long address)
static void compute_alias(struct cache_info *c)
{
+#ifdef CONFIG_MMU
c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
+#else
+ c->alias_mask = 0;
+#endif
c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
}