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authorSam Ravnborg <sam@ravnborg.org>2012-05-20 19:27:53 +0400
committerDavid S. Miller <davem@davemloft.net>2012-05-21 00:33:36 +0400
commit1edc17832d8f49a0263d364c453ea35da0e4e2a6 (patch)
tree02c460fef4abb53a1b1ebe493b1e731ef36f6f26 /arch/sparc/include/asm/cacheflush_64.h
parent9cd5f82246b724aae402959bffe0441b45a01a1c (diff)
downloadlinux-1edc17832d8f49a0263d364c453ea35da0e4e2a6.tar.xz
sparc32: use flushi when run-time patching in per_cpu_patch
Davis S. Miller wrote: " The way we do that now is overkill. We only needed to use the MMU cache ops when we had sun4c around because sun4c lacked support for the "flush" instruction. But all sun4m and later chips have it so we can use it unconditionally. So in the per_cpu_patch() code, get rid of the cache ops invocation, and instead execute a "flush %reg" after each of the instruction patch assignments, where %reg is set to the address of the instruction that was stored into. Perhaps take the flushi() definition from asm/cacheflush_64.h and place it into asm/cacheflush.h, then you can simply use that. " Implemented as per suggestion. Moved run-time patching before we call paging_init(), so helper methods in paging_init() may utilise run-time patching too. Signed-off-by: Sam Ravnborg <sam@ravnborg.org> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc/include/asm/cacheflush_64.h')
-rw-r--r--arch/sparc/include/asm/cacheflush_64.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/sparc/include/asm/cacheflush_64.h b/arch/sparc/include/asm/cacheflush_64.h
index 2efea2ff88b7..301736d9e7a1 100644
--- a/arch/sparc/include/asm/cacheflush_64.h
+++ b/arch/sparc/include/asm/cacheflush_64.h
@@ -8,9 +8,6 @@
#include <linux/mm.h>
/* Cache flush operations. */
-
-
-#define flushi(addr) __asm__ __volatile__ ("flush %0" : : "r" (addr) : "memory")
#define flushw_all() __asm__ __volatile__("flushw")
extern void __flushw_user(void);