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authorChris Metcalf <cmetcalf@tilera.com>2010-06-26 01:03:27 +0400
committerChris Metcalf <cmetcalf@tilera.com>2010-07-06 21:41:46 +0400
commitc78095bd8c77fca2619769ff8efb639fd100e373 (patch)
tree9841462486a97a3733f0e5b789e8f6dce47ca62f /arch/tile/lib
parent2db098278118ed58f4b407ceda691e349df043ce (diff)
downloadlinux-c78095bd8c77fca2619769ff8efb639fd100e373.tar.xz
arch/tile: Split the icache flush code off to a generic <arch> header.
This code is used in other places in our system than in Linux, so to share it we now implement it as an inline function in our low-level <arch> headers, and instantiate it in one file in Linux's arch/tile/lib. The file is now cacheflush.c and is C code rather than the strangely-named and assembler-implemented __invalidate_icache.S. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com> Acked-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/tile/lib')
-rw-r--r--arch/tile/lib/Makefile2
-rw-r--r--arch/tile/lib/__invalidate_icache.S106
-rw-r--r--arch/tile/lib/cacheflush.c23
3 files changed, 24 insertions, 107 deletions
diff --git a/arch/tile/lib/Makefile b/arch/tile/lib/Makefile
index ea9c209d33fb..438af38bc9eb 100644
--- a/arch/tile/lib/Makefile
+++ b/arch/tile/lib/Makefile
@@ -2,7 +2,7 @@
# Makefile for TILE-specific library files..
#
-lib-y = checksum.o cpumask.o delay.o __invalidate_icache.o \
+lib-y = cacheflush.o checksum.o cpumask.o delay.o \
mb_incoherent.o uaccess.o \
memcpy_$(BITS).o memchr_$(BITS).o memmove_$(BITS).o memset_$(BITS).o \
strchr_$(BITS).o strlen_$(BITS).o
diff --git a/arch/tile/lib/__invalidate_icache.S b/arch/tile/lib/__invalidate_icache.S
deleted file mode 100644
index 92e705059127..000000000000
--- a/arch/tile/lib/__invalidate_icache.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- * A routine for synchronizing the instruction and data caches.
- * Useful for self-modifying code.
- *
- * r0 holds the buffer address
- * r1 holds the size in bytes
- */
-
-#include <arch/chip.h>
-#include <feedback.h>
-
-#if defined(__NEWLIB__) || defined(__BME__)
-#include <sys/page.h>
-#else
-#include <asm/page.h>
-#endif
-
-#ifdef __tilegx__
-/* Share code among Tile family chips but adjust opcodes appropriately. */
-#define slt cmpltu
-#define bbst blbst
-#define bnezt bnzt
-#endif
-
-#if defined(__tilegx__) && __SIZEOF_POINTER__ == 4
-/* Force 32-bit ops so pointers wrap around appropriately. */
-#define ADD_PTR addx
-#define ADDI_PTR addxi
-#else
-#define ADD_PTR add
-#define ADDI_PTR addi
-#endif
-
- .section .text.__invalidate_icache, "ax"
- .global __invalidate_icache
- .type __invalidate_icache,@function
- .hidden __invalidate_icache
- .align 8
-__invalidate_icache:
- FEEDBACK_ENTER(__invalidate_icache)
- {
- ADD_PTR r1, r0, r1 /* end of buffer */
- blez r1, .Lexit /* skip out if size <= 0 */
- }
- {
- ADDI_PTR r1, r1, -1 /* point to last byte to flush */
- andi r0, r0, -CHIP_L1I_LINE_SIZE() /* align to cache-line size */
- }
- {
- andi r1, r1, -CHIP_L1I_LINE_SIZE() /* last cache line to flush */
- mf
- }
-#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
- {
- moveli r4, CHIP_L1I_CACHE_SIZE() / PAGE_SIZE /* loop counter */
- move r2, r0 /* remember starting address */
- }
-#endif
- drain
- {
- slt r3, r0, r1 /* set up loop invariant */
-#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
- moveli r6, PAGE_SIZE
-#endif
- }
-.Lentry:
- {
- icoh r0
- ADDI_PTR r0, r0, CHIP_L1I_LINE_SIZE() /* advance buffer */
- }
- {
- slt r3, r0, r1 /* check if buffer < buffer + size */
- bbst r3, .Lentry /* loop if buffer < buffer + size */
- }
-#if CHIP_L1I_CACHE_SIZE() > PAGE_SIZE
- {
- ADD_PTR r2, r2, r6
- ADD_PTR r1, r1, r6
- }
- {
- move r0, r2
- addi r4, r4, -1
- }
- {
- slt r3, r0, r1 /* set up loop invariant */
- bnezt r4, .Lentry
- }
-#endif
- drain
-.Lexit:
- jrp lr
-
-.Lend___invalidate_icache:
- .size __invalidate_icache, \
- .Lend___invalidate_icache - __invalidate_icache
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
new file mode 100644
index 000000000000..11b6164c2097
--- /dev/null
+++ b/arch/tile/lib/cacheflush.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2010 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <asm/page.h>
+#include <asm/cacheflush.h>
+#include <arch/icache.h>
+
+
+void __flush_icache_range(unsigned long start, unsigned long end)
+{
+ invalidate_icache((const void *)start, end - start, PAGE_SIZE);
+}