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| author | Jinank Jain <jinankjain@linux.microsoft.com> | 2023-01-02 10:12:52 +0300 |
|---|---|---|
| committer | Wei Liu <wei.liu@kernel.org> | 2023-01-17 16:36:43 +0300 |
| commit | 7fec185a56f45b98d9547982370c2ab33f0f72b5 (patch) | |
| tree | e090edfd6a998b4322f1bc4969351883ba977486 /arch/x86/include/asm/hyperv-tlfs.h | |
| parent | c4bdf94f97c86bdee8bacc87f8f85dc67866c928 (diff) | |
| download | linux-7fec185a56f45b98d9547982370c2ab33f0f72b5.tar.xz | |
Drivers: hv: Setup synic registers in case of nested root partition
Child partitions are free to allocate SynIC message and event page but in
case of root partition it must use the pages allocated by Microsoft
Hypervisor (MSHV). Base address for these pages can be found using
synthetic MSRs exposed by MSHV. There is a slight difference in those MSRs
for nested vs non-nested root partition.
Signed-off-by: Jinank Jain <jinankjain@linux.microsoft.com>
Reviewed-by: Nuno Das Neves <nunodasneves@linux.microsoft.com>
Reviewed-by: Michael Kelley <mikelley@microsoft.com>
Link: https://lore.kernel.org/r/cb951fb1ad6814996fc54f4a255c5841a20a151f.1672639707.git.jinankjain@linux.microsoft.com
Signed-off-by: Wei Liu <wei.liu@kernel.org>
Diffstat (limited to 'arch/x86/include/asm/hyperv-tlfs.h')
| -rw-r--r-- | arch/x86/include/asm/hyperv-tlfs.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/x86/include/asm/hyperv-tlfs.h b/arch/x86/include/asm/hyperv-tlfs.h index 724a2589c0e7..271d081dc251 100644 --- a/arch/x86/include/asm/hyperv-tlfs.h +++ b/arch/x86/include/asm/hyperv-tlfs.h @@ -228,6 +228,17 @@ enum hv_isolation_type { #define HV_REGISTER_SINT15 0x4000009F /* + * Define synthetic interrupt controller model specific registers for + * nested hypervisor. + */ +#define HV_REGISTER_NESTED_SCONTROL 0x40001080 +#define HV_REGISTER_NESTED_SVERSION 0x40001081 +#define HV_REGISTER_NESTED_SIEFP 0x40001082 +#define HV_REGISTER_NESTED_SIMP 0x40001083 +#define HV_REGISTER_NESTED_EOM 0x40001084 +#define HV_REGISTER_NESTED_SINT0 0x40001090 + +/* * Synthetic Timer MSRs. Four timers per vcpu. */ #define HV_REGISTER_STIMER0_CONFIG 0x400000B0 |