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authorKuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>2013-10-18 02:35:29 +0400
committerH. Peter Anvin <hpa@linux.intel.com>2013-10-18 03:40:47 +0400
commit712b6aa8731a7e148298c58cea66a5209c659e3c (patch)
tree0949764eead1f8cef611277141c5684c55cfa957 /arch/x86/include/asm/intel-mid.h
parent6c21b176a93ffaa8023555107167379ccdc6b71f (diff)
downloadlinux-712b6aa8731a7e148298c58cea66a5209c659e3c.tar.xz
intel_mid: Renamed *mrst* to *intel_mid*
mrst is used as common name to represent all intel_mid type soc's. But moorsetwon is just one of the intel_mid soc. So renamed them to use intel_mid. This patch mainly renames the variables and related functions that uses *mrst* prefix with *intel_mid*. To ensure that there are no functional changes, I have compared the objdump of related files before and after rename and found the only difference is symbol and name changes. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Link: http://lkml.kernel.org/r/1382049336-21316-6-git-send-email-david.a.cohen@linux.intel.com Signed-off-by: David Cohen <david.a.cohen@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Diffstat (limited to 'arch/x86/include/asm/intel-mid.h')
-rw-r--r--arch/x86/include/asm/intel-mid.h26
1 files changed, 13 insertions, 13 deletions
diff --git a/arch/x86/include/asm/intel-mid.h b/arch/x86/include/asm/intel-mid.h
index cc79a4f7aeed..beb7a5f1862a 100644
--- a/arch/x86/include/asm/intel-mid.h
+++ b/arch/x86/include/asm/intel-mid.h
@@ -13,7 +13,7 @@
#include <linux/sfi.h>
-extern int pci_mrst_init(void);
+extern int intel_mid_pci_init(void);
extern int __init sfi_parse_mrtc(struct sfi_table_header *table);
extern int sfi_mrtc_num;
extern struct sfi_rtc_table_entry sfi_mrtc_array[];
@@ -25,33 +25,33 @@ extern struct sfi_rtc_table_entry sfi_mrtc_array[];
* we treat Medfield/Penwell as a variant of Moorestown. Penwell can be
* identified via MSRs.
*/
-enum mrst_cpu_type {
+enum intel_mid_cpu_type {
/* 1 was Moorestown */
- MRST_CPU_CHIP_PENWELL = 2,
+ INTEL_MID_CPU_CHIP_PENWELL = 2,
};
-extern enum mrst_cpu_type __mrst_cpu_chip;
+extern enum intel_mid_cpu_type __intel_mid_cpu_chip;
#ifdef CONFIG_X86_INTEL_MID
-static inline enum mrst_cpu_type mrst_identify_cpu(void)
+static inline enum intel_mid_cpu_type intel_mid_identify_cpu(void)
{
- return __mrst_cpu_chip;
+ return __intel_mid_cpu_chip;
}
#else /* !CONFIG_X86_INTEL_MID */
-#define mrst_identify_cpu() (0)
+#define intel_mid_identify_cpu() (0)
#endif /* !CONFIG_X86_INTEL_MID */
-enum mrst_timer_options {
- MRST_TIMER_DEFAULT,
- MRST_TIMER_APBT_ONLY,
- MRST_TIMER_LAPIC_APBT,
+enum intel_mid_timer_options {
+ INTEL_MID_TIMER_DEFAULT,
+ INTEL_MID_TIMER_APBT_ONLY,
+ INTEL_MID_TIMER_LAPIC_APBT,
};
-extern enum mrst_timer_options mrst_timer_options;
+extern enum intel_mid_timer_options intel_mid_timer_options;
/*
* Penwell uses spread spectrum clock, so the freq number is not exactly
@@ -76,6 +76,6 @@ extern void intel_scu_devices_destroy(void);
#define MRST_VRTC_MAP_SZ (1024)
/*#define MRST_VRTC_PGOFFSET (0xc00) */
-extern void mrst_rtc_init(void);
+extern void intel_mid_rtc_init(void);
#endif /* _ASM_X86_INTEL_MID_H */