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| author | Paolo Bonzini <pbonzini@redhat.com> | 2018-08-05 17:07:46 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2018-08-05 18:10:19 +0300 |
| commit | 8e0b2b916662e09dd4d09e5271cdf214c6b80e62 (patch) | |
| tree | 77e5da72764da3c8ead7c72391a369f48adfb606 /arch/x86/include/asm/msr-index.h | |
| parent | ea156d192f5257a5bf393d33910d3b481bf8a401 (diff) | |
| download | linux-8e0b2b916662e09dd4d09e5271cdf214c6b80e62.tar.xz | |
x86/speculation: Use ARCH_CAPABILITIES to skip L1D flush on vmentry
Bit 3 of ARCH_CAPABILITIES tells a hypervisor that L1D flush on vmentry is
not needed. Add a new value to enum vmx_l1d_flush_state, which is used
either if there is no L1TF bug at all, or if bit 3 is set in ARCH_CAPABILITIES.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 0e7517089b80..4731f0cf97c5 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -70,6 +70,7 @@ #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ +#define ARCH_CAP_SKIP_VMENTRY_L1DFLUSH (1 << 3) /* Skip L1D flush on vmentry */ #define ARCH_CAP_SSB_NO (1 << 4) /* * Not susceptible to Speculative Store Bypass * attack, so no Speculative Store Bypass |