diff options
| author | Peter Zijlstra (Intel) <peterz@infradead.org> | 2019-03-06 00:23:17 +0300 |
|---|---|---|
| committer | Thomas Gleixner <tglx@linutronix.de> | 2019-03-06 11:25:41 +0300 |
| commit | 52f64909409c17adf54fcf5f9751e0544ca3a6b4 (patch) | |
| tree | e61af1fcb70735394b1269070d5a763c52cf604c /arch/x86/include/asm/msr-index.h | |
| parent | 11f8b2d65ca9029591c8df26bb6bd063c312b7fe (diff) | |
| download | linux-52f64909409c17adf54fcf5f9751e0544ca3a6b4.tar.xz | |
x86: Add TSX Force Abort CPUID/MSR
Skylake systems will receive a microcode update to address a TSX
errata. This microcode will (by default) clobber PMC3 when TSX
instructions are (speculatively or not) executed.
It also provides an MSR to cause all TSX transaction to abort and
preserve PMC3.
Add the CPUID enumeration and MSR definition.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
| -rw-r--r-- | arch/x86/include/asm/msr-index.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 8e40c2446fd1..ca5bc0eacb95 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -666,6 +666,12 @@ #define MSR_IA32_TSC_DEADLINE 0x000006E0 + +#define MSR_TSX_FORCE_ABORT 0x0000010F + +#define MSR_TFA_RTM_FORCE_ABORT_BIT 0 +#define MSR_TFA_RTM_FORCE_ABORT BIT_ULL(MSR_TFA_RTM_FORCE_ABORT_BIT) + /* P4/Xeon+ specific */ #define MSR_IA32_MCG_EAX 0x00000180 #define MSR_IA32_MCG_EBX 0x00000181 |