diff options
| author | Like Xu <like.xu@linux.intel.com> | 2021-02-01 08:10:36 +0300 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2021-02-04 13:27:25 +0300 |
| commit | e6209a3bef793e8fe29c873a7612023916eaa611 (patch) | |
| tree | b885d145d233977d0b6e5105d5194d5a5a6ad3ab /arch/x86/kvm/vmx/capabilities.h | |
| parent | 9254beaafd12e27d48149fab3b16db372bc90ad7 (diff) | |
| download | linux-e6209a3bef793e8fe29c873a7612023916eaa611.tar.xz | |
KVM: vmx/pmu: Emulate legacy freezing LBRs on virtual PMI
The current vPMU only supports Architecture Version 2. According to
Intel SDM "17.4.7 Freezing LBR and Performance Counters on PMI", if
IA32_DEBUGCTL.Freeze_LBR_On_PMI = 1, the LBR is frozen on the virtual
PMI and the KVM would emulate to clear the LBR bit (bit 0) in
IA32_DEBUGCTL. Also, guest needs to re-enable IA32_DEBUGCTL.LBR
to resume recording branches.
Signed-off-by: Like Xu <like.xu@linux.intel.com>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Message-Id: <20210201051039.255478-9-like.xu@linux.intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'arch/x86/kvm/vmx/capabilities.h')
| -rw-r--r-- | arch/x86/kvm/vmx/capabilities.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index 787edd8c1fc7..8e6179586e27 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -21,6 +21,8 @@ extern int __read_mostly pt_mode; #define PMU_CAP_FW_WRITES (1ULL << 13) #define PMU_CAP_LBR_FMT 0x3f +#define DEBUGCTLMSR_LBR_MASK (DEBUGCTLMSR_LBR | DEBUGCTLMSR_FREEZE_LBRS_ON_PMI) + struct nested_vmx_msrs { /* * We only store the "true" versions of the VMX capability MSRs. We @@ -390,7 +392,7 @@ static inline u64 vmx_supported_debugctl(void) u64 debugctl = 0; if (vmx_get_perf_capabilities() & PMU_CAP_LBR_FMT) - debugctl |= DEBUGCTLMSR_LBR; + debugctl |= DEBUGCTLMSR_LBR_MASK; return debugctl; } |