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| author | H. Peter Anvin (Intel) <hpa@zytor.com> | 2023-01-12 10:20:28 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2023-01-12 15:06:20 +0300 |
| commit | 660569472dd7ac64571375b6727c3f2c1d70ba40 (patch) | |
| tree | 17d03cf148ec334650ff214b47b5b2c61baff874 /arch/x86/lib | |
| parent | 0125acda7d76b943ca55811df40ed6ec0ecf670f (diff) | |
| download | linux-660569472dd7ac64571375b6727c3f2c1d70ba40.tar.xz | |
x86/cpufeature: Add the CPU feature bit for LKGS
Add the CPU feature bit for LKGS (Load "Kernel" GS).
LKGS instruction is introduced with Intel FRED (flexible return and
event delivery) specification. Search for the latest FRED spec in most
search engines with this search pattern:
site:intel.com FRED (flexible return and event delivery) specification
LKGS behaves like the MOV to GS instruction except that it loads
the base address into the IA32_KERNEL_GS_BASE MSR instead of the
GS segment’s descriptor cache, which is exactly what Linux kernel
does to load a user level GS base. Thus, with LKGS, there is no
need to SWAPGS away from the kernel GS base.
[ mingo: Minor tweaks to the description. ]
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20230112072032.35626-2-xin3.li@intel.com
Diffstat (limited to 'arch/x86/lib')
0 files changed, 0 insertions, 0 deletions