diff options
author | Max Filippov <jcmvbkbc@gmail.com> | 2019-05-13 06:28:25 +0300 |
---|---|---|
committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-07-08 20:04:48 +0300 |
commit | d6d5f19e21d98c0607ff029e4e2e508d4cdd1d5a (patch) | |
tree | 1780d36ac99c16f8ed506948a020017e84a89a9f /arch/xtensa/mm/misc.S | |
parent | 831c4f3da83e260df943dfb982d77cef5cba2c49 (diff) | |
download | linux-d6d5f19e21d98c0607ff029e4e2e508d4cdd1d5a.tar.xz |
xtensa: abstract 'entry' and 'retw' in assembly code
Provide abi_entry, abi_entry_default, abi_ret and abi_ret_default macros
that allocate aligned stack frame in windowed and call0 ABIs.
Provide XTENSA_SPILL_STACK_RESERVE macro that specifies required stack
frame size when register spilling is involved.
Replace all uses of 'entry' and 'retw' with the above macros.
This makes most of the xtensa assembly code ready for XEA3 and call0 ABI.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/mm/misc.S')
-rw-r--r-- | arch/xtensa/mm/misc.S | 78 |
1 files changed, 39 insertions, 39 deletions
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S index 11a01c3e9cea..6aa036c427c3 100644 --- a/arch/xtensa/mm/misc.S +++ b/arch/xtensa/mm/misc.S @@ -30,7 +30,7 @@ ENTRY(clear_page) - entry a1, 16 + abi_entry_default movi a3, 0 __loopi a2, a7, PAGE_SIZE, 32 @@ -44,7 +44,7 @@ ENTRY(clear_page) s32i a3, a2, 28 __endla a2, a7, 32 - retw + abi_ret_default ENDPROC(clear_page) @@ -57,7 +57,7 @@ ENDPROC(clear_page) ENTRY(copy_page) - entry a1, 16 + abi_entry_default __loopi a2, a4, PAGE_SIZE, 32 @@ -86,7 +86,7 @@ ENTRY(copy_page) __endl a2, a4 - retw + abi_ret_default ENDPROC(copy_page) @@ -116,7 +116,7 @@ ENTRY(__tlbtemp_mapping_start) ENTRY(clear_page_alias) - entry a1, 32 + abi_entry_default /* Skip setting up a temporary DTLB if not aliased low page. */ @@ -144,14 +144,14 @@ ENTRY(clear_page_alias) __endla a2, a7, 32 bnez a6, 1f - retw + abi_ret_default /* We need to invalidate the temporary idtlb entry, if any. */ 1: idtlb a4 dsync - retw + abi_ret_default ENDPROC(clear_page_alias) @@ -164,7 +164,7 @@ ENDPROC(clear_page_alias) ENTRY(copy_page_alias) - entry a1, 32 + abi_entry_default /* Skip setting up a temporary DTLB for destination if not aliased. */ @@ -221,19 +221,19 @@ ENTRY(copy_page_alias) bnez a6, 1f bnez a7, 2f - retw + abi_ret_default 1: addi a2, a2, -PAGE_SIZE idtlb a2 dsync bnez a7, 2f - retw + abi_ret_default 2: addi a3, a3, -PAGE_SIZE+1 idtlb a3 dsync - retw + abi_ret_default ENDPROC(copy_page_alias) @@ -248,7 +248,7 @@ ENDPROC(copy_page_alias) ENTRY(__flush_invalidate_dcache_page_alias) - entry sp, 16 + abi_entry_default movi a7, 0 # required for exception handler addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) @@ -261,7 +261,7 @@ ENTRY(__flush_invalidate_dcache_page_alias) idtlb a4 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_page_alias) @@ -272,7 +272,7 @@ ENDPROC(__flush_invalidate_dcache_page_alias) ENTRY(__invalidate_dcache_page_alias) - entry sp, 16 + abi_entry_default movi a7, 0 # required for exception handler addi a6, a3, (PAGE_KERNEL | _PAGE_HW_WRITE) @@ -285,7 +285,7 @@ ENTRY(__invalidate_dcache_page_alias) idtlb a4 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_page_alias) #endif @@ -296,7 +296,7 @@ ENTRY(__tlbtemp_mapping_itlb) ENTRY(__invalidate_icache_page_alias) - entry sp, 16 + abi_entry_default addi a6, a3, (PAGE_KERNEL_EXEC | _PAGE_HW_WRITE) mov a4, a2 @@ -307,7 +307,7 @@ ENTRY(__invalidate_icache_page_alias) iitlb a4 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_page_alias) @@ -325,12 +325,12 @@ ENTRY(__tlbtemp_mapping_end) ENTRY(__invalidate_icache_page) - entry sp, 16 + abi_entry_default ___invalidate_icache_page a2 a3 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_page) @@ -340,12 +340,12 @@ ENDPROC(__invalidate_icache_page) ENTRY(__invalidate_dcache_page) - entry sp, 16 + abi_entry_default ___invalidate_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_page) @@ -355,12 +355,12 @@ ENDPROC(__invalidate_dcache_page) ENTRY(__flush_invalidate_dcache_page) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_page) @@ -370,12 +370,12 @@ ENDPROC(__flush_invalidate_dcache_page) ENTRY(__flush_dcache_page) - entry sp, 16 + abi_entry_default ___flush_dcache_page a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_dcache_page) @@ -385,12 +385,12 @@ ENDPROC(__flush_dcache_page) ENTRY(__invalidate_icache_range) - entry sp, 16 + abi_entry_default ___invalidate_icache_range a2 a3 a4 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_range) @@ -400,12 +400,12 @@ ENDPROC(__invalidate_icache_range) ENTRY(__flush_invalidate_dcache_range) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_range a2 a3 a4 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_range) @@ -415,12 +415,12 @@ ENDPROC(__flush_invalidate_dcache_range) ENTRY(__flush_dcache_range) - entry sp, 16 + abi_entry_default ___flush_dcache_range a2 a3 a4 dsync - retw + abi_ret_default ENDPROC(__flush_dcache_range) @@ -430,11 +430,11 @@ ENDPROC(__flush_dcache_range) ENTRY(__invalidate_dcache_range) - entry sp, 16 + abi_entry_default ___invalidate_dcache_range a2 a3 a4 - retw + abi_ret_default ENDPROC(__invalidate_dcache_range) @@ -444,12 +444,12 @@ ENDPROC(__invalidate_dcache_range) ENTRY(__invalidate_icache_all) - entry sp, 16 + abi_entry_default ___invalidate_icache_all a2 a3 isync - retw + abi_ret_default ENDPROC(__invalidate_icache_all) @@ -459,12 +459,12 @@ ENDPROC(__invalidate_icache_all) ENTRY(__flush_invalidate_dcache_all) - entry sp, 16 + abi_entry_default ___flush_invalidate_dcache_all a2 a3 dsync - retw + abi_ret_default ENDPROC(__flush_invalidate_dcache_all) @@ -474,11 +474,11 @@ ENDPROC(__flush_invalidate_dcache_all) ENTRY(__invalidate_dcache_all) - entry sp, 16 + abi_entry_default ___invalidate_dcache_all a2 a3 dsync - retw + abi_ret_default ENDPROC(__invalidate_dcache_all) |