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author | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-04 19:38:26 +0400 |
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committer | Linus Torvalds <torvalds@linux-foundation.org> | 2013-09-04 19:38:26 +0400 |
commit | ac3c1c4f1c77190408162aee559c655090597072 (patch) | |
tree | 6c0e1ddbada6d6dbfb59b7f8d766dfd38b7321f1 /arch | |
parent | 5e0b3a4e88012d259e8b2c0f02f393c79686daf9 (diff) | |
parent | cfb6d656d569510ac9239583ce09e4c92ad54719 (diff) | |
download | linux-ac3c1c4f1c77190408162aee559c655090597072.tar.xz |
Merge branch 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull timer changes from Ingo Molnar:
"Various clocksource driver updates: extend the core with memory mapped
hardware (mmio) support and add new (ARM) Moxart SoC and sun4i
hardware support"
* 'timers-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
clocksource: arch_timer: Add support for memory mapped timers
clocksource: arch_timer: Push the read/write wrappers deeper
Documentation: Add memory mapped ARM architected timer binding
clocksource: arch_timer: Pass clock event to set_mode callback
clocksource: arch_timer: Make register accessors less error-prone
ARM: clocksource: moxart: documentation: Update device tree bindings document
ARM: clocksource: moxart: Add bitops.h include
ARM: clocksource: moxart: documentation: Fix device tree bindings document
ARM: clocksource: Add support for MOXA ART SoCs
clocksource: cadence_ttc: Reuse clocksource as sched_clock
clocksource: cadence_ttc: Remove unused header
clocksource: sun4i: Fix bug when switching from periodic to oneshot modes
clocksource: sun4i: Cleanup parent clock setup
clocksource: sun4i: Remove TIMER_SCAL variable
clocksource: sun4i: Factor out some timer code
clocksource: sun4i: Fix the next event code
clocksource: sun4i: Don't forget to enable the clock we use
clocksource: sun4i: Add clocksource and sched clock drivers
clocksource: sun4i: rename AUTORELOAD define to RELOAD
clocksource: sun4i: Wrap macros arguments in parenthesis
...
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/include/asm/arch_timer.h | 14 | ||||
-rw-r--r-- | arch/arm64/include/asm/arch_timer.h | 23 |
2 files changed, 15 insertions, 22 deletions
diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index e406d575c94f..5665134bfa3e 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -17,7 +17,8 @@ int arch_timer_arch_init(void); * nicely work out which register we want, and chuck away the rest of * the code. At least it does so with a recent GCC (4.6.3). */ -static inline void arch_timer_reg_write(const int access, const int reg, u32 val) +static __always_inline +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) { if (access == ARCH_TIMER_PHYS_ACCESS) { switch (reg) { @@ -28,9 +29,7 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); break; } - } - - if (access == ARCH_TIMER_VIRT_ACCESS) { + } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { case ARCH_TIMER_REG_CTRL: asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); @@ -44,7 +43,8 @@ static inline void arch_timer_reg_write(const int access, const int reg, u32 val isb(); } -static inline u32 arch_timer_reg_read(const int access, const int reg) +static __always_inline +u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) { u32 val = 0; @@ -57,9 +57,7 @@ static inline u32 arch_timer_reg_read(const int access, const int reg) asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val)); break; } - } - - if (access == ARCH_TIMER_VIRT_ACCESS) { + } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { case ARCH_TIMER_REG_CTRL: asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index 98abd476992d..c9f1d2816c2b 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -26,7 +26,13 @@ #include <clocksource/arm_arch_timer.h> -static inline void arch_timer_reg_write(int access, int reg, u32 val) +/* + * These register accessors are marked inline so the compiler can + * nicely work out which register we want, and chuck away the rest of + * the code. + */ +static __always_inline +void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val) { if (access == ARCH_TIMER_PHYS_ACCESS) { switch (reg) { @@ -36,8 +42,6 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val) case ARCH_TIMER_REG_TVAL: asm volatile("msr cntp_tval_el0, %0" : : "r" (val)); break; - default: - BUILD_BUG(); } } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { @@ -47,17 +51,14 @@ static inline void arch_timer_reg_write(int access, int reg, u32 val) case ARCH_TIMER_REG_TVAL: asm volatile("msr cntv_tval_el0, %0" : : "r" (val)); break; - default: - BUILD_BUG(); } - } else { - BUILD_BUG(); } isb(); } -static inline u32 arch_timer_reg_read(int access, int reg) +static __always_inline +u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg) { u32 val; @@ -69,8 +70,6 @@ static inline u32 arch_timer_reg_read(int access, int reg) case ARCH_TIMER_REG_TVAL: asm volatile("mrs %0, cntp_tval_el0" : "=r" (val)); break; - default: - BUILD_BUG(); } } else if (access == ARCH_TIMER_VIRT_ACCESS) { switch (reg) { @@ -80,11 +79,7 @@ static inline u32 arch_timer_reg_read(int access, int reg) case ARCH_TIMER_REG_TVAL: asm volatile("mrs %0, cntv_tval_el0" : "=r" (val)); break; - default: - BUILD_BUG(); } - } else { - BUILD_BUG(); } return val; |