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authorSimon Horman <horms@verge.net.au>2012-11-13 06:42:28 +0400
committerSimon Horman <horms@verge.net.au>2012-11-13 06:42:28 +0400
commitd5bea23c82c724231d5077a240887748a5bcd25a (patch)
tree8007bd9f292f19d5a26aa63d3d30c9b30000e382 /arch
parent40937f7460041864c003d49b1f2ddcb32d5044f3 (diff)
downloadlinux-d5bea23c82c724231d5077a240887748a5bcd25a.tar.xz
Revert "ARM: shmobile: sh73a0: Replace modify_scu_cpu_psr with scu_power_mode"
This reverts commit e721295185535ed6ef4711eba156fbf5c24f9c5e. The code changes the flags of the wrong cpus - which breaks the whole bootup of secondary CPUs. Cc: Bastian Hecht <hechtb@gmail.com> Signed-off-by: Simon Horman <horms@verge.net.au>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c23
1 files changed, 21 insertions, 2 deletions
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index 96ddb97babbe..624f00f70abf 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -41,6 +41,9 @@ static void __iomem *scu_base_addr(void)
return (void __iomem *)0xf0000000;
}
+static DEFINE_SPINLOCK(scu_lock);
+static unsigned long tmp;
+
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
void __init sh73a0_register_twd(void)
@@ -49,6 +52,20 @@ void __init sh73a0_register_twd(void)
}
#endif
+static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
+{
+ void __iomem *scu_base = scu_base_addr();
+
+ spin_lock(&scu_lock);
+ tmp = __raw_readl(scu_base + 8);
+ tmp &= ~clr;
+ tmp |= set;
+ spin_unlock(&scu_lock);
+
+ /* disable cache coherency after releasing the lock */
+ __raw_writel(tmp, scu_base + 8);
+}
+
static unsigned int __init sh73a0_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
@@ -66,7 +83,7 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
- scu_power_mode(scu_base_addr(), 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
__raw_writel(1 << cpu, WUPCR); /* wake up */
@@ -78,6 +95,8 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
{
+ int cpu = cpu_logical_map(0);
+
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp.S) */
@@ -85,7 +104,7 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
__raw_writel(__pa(shmobile_secondary_vector), SBAR);
/* enable cache coherency on CPU0 */
- scu_power_mode(scu_base_addr(), 0);
+ modify_scu_cpu_psr(0, 3 << (cpu * 8));
}
static void __init sh73a0_smp_init_cpus(void)