diff options
| author | Jiaxun Yang <jiaxun.yang@flygoat.com> | 2024-06-16 16:25:02 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-06-27 14:52:30 +0300 |
| commit | e634ba81ce4187d653cd4942575920abff25db65 (patch) | |
| tree | 8a081261bdeb40ea82c1e7c380274051dac55fa6 /arch | |
| parent | 2c48087fab46994ce0e33a186d1252a8f98592db (diff) | |
| download | linux-e634ba81ce4187d653cd4942575920abff25db65.tar.xz | |
MIPS: mipsmtregs: Fix target register for MFTC0
commit 4a3e37b3caea817199757a0b13aa53dd7c9376c8 upstream.
Target register of mftc0 should be __res instead of $1, this is
a leftover from old .insn code.
Fixes: dd6d29a61489 ("MIPS: Implement microMIPS MT ASE helpers")
Cc: stable@vger.kernel.org
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/include/asm/mipsmtregs.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h index 30e86861c206..b1ee3c48e84b 100644 --- a/arch/mips/include/asm/mipsmtregs.h +++ b/arch/mips/include/asm/mipsmtregs.h @@ -322,7 +322,7 @@ static inline void ehb(void) " .set push \n" \ " .set "MIPS_ISA_LEVEL" \n" \ _ASM_SET_MFTC0 \ - " mftc0 $1, " #rt ", " #sel " \n" \ + " mftc0 %0, " #rt ", " #sel " \n" \ _ASM_UNSET_MFTC0 \ " .set pop \n" \ : "=r" (__res)); \ |